From: Clifford Wolf <clifford@clifford.at>
Date: Thu, 30 Oct 2014 08:12:55 +0000 (+0100)
Subject: Improved nomem2reg documentation
X-Git-Tag: yosys-0.4~16
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ac8f4d298b3cc351fa0658857e11069a67adb7ba;p=yosys.git

Improved nomem2reg documentation
---

diff --git a/README b/README
index 1eb6f10aa..d90a11935 100644
--- a/README
+++ b/README
@@ -248,7 +248,10 @@ Verilog Attributes and non-standard features
   is strongly recommended instead).
 
 - The "nomem2reg" attribute on modules or arrays prohibits the
-  automatic early conversion of arrays to separate registers.
+  automatic early conversion of arrays to separate registers. This
+  is potentially dangerous. Usually the front-end has good reasons
+  for converting an array to a list of registers. Prohibiting this
+  step will likely result in incorrect synthesis results.
 
 - The "mem2reg" attribute on modules or arrays forces the early
   conversion of arrays to separate registers.