From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 28 Apr 2019 20:04:34 +0000 (-0700)
Subject: Copy with 1'bx padding in $shiftx
X-Git-Tag: yosys-0.9~164
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=acafcdc94dc148b2bf9c8faef173e5b2b54e1ac5;p=yosys.git

Copy with 1'bx padding in $shiftx
---

diff --git a/passes/techmap/shregmap.cc b/passes/techmap/shregmap.cc
index a541b33be..75eedfbcc 100644
--- a/passes/techmap/shregmap.cc
+++ b/passes/techmap/shregmap.cc
@@ -178,7 +178,17 @@ struct ShregmapTechXilinx7 : ShregmapTech
 
 		// Only map if $shiftx exclusively covers the shift register
 		if (shiftx->type == "$shiftx") {
-			if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
+			if (GetSize(taps) > shiftx->getParam("\\A_WIDTH").as_int())
+				return false;
+			// Due to padding the most significant bits of A may be 1'bx,
+			//   and if so, discount them
+			if (GetSize(taps) < shiftx->getParam("\\A_WIDTH").as_int()) {
+				const SigSpec A = shiftx->getPort("\\A");
+				const int A_width = shiftx->getParam("\\A_WIDTH").as_int();
+				for (int i = GetSize(taps); i < A_width; ++i)
+					if (A[i] != RTLIL::Sx) return false;
+			}
+			else if (GetSize(taps) != shiftx->getParam("\\A_WIDTH").as_int())
 				return false;
 		}
 		else if (shiftx->type == "$mux") {