From: Miodrag Milanovic <mmicko@gmail.com>
Date: Sat, 14 Mar 2020 13:33:44 +0000 (+0100)
Subject: Fix invalid verilog syntax
X-Git-Tag: working-ls180~751
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=acb341745d436987ad764c9198ff0c6ab63c572c;p=yosys.git

Fix invalid verilog syntax
---

diff --git a/techlibs/common/gate2lut.v b/techlibs/common/gate2lut.v
index 99c123f4a..15cea3d8d 100644
--- a/techlibs/common/gate2lut.v
+++ b/techlibs/common/gate2lut.v
@@ -79,7 +79,7 @@ module _90_lut_mux (A, B, S, Y);
         //     A 1010 1010
         //     B 1100 1100
         //     S 1111 0000
-        .LUT(8'b_1100_1010)
+        .LUT(8'b 1100_1010)
     ) lut (
         .A(AA),
         .Y(Y)