From: Tim Newsome <tim@sifive.com>
Date: Mon, 3 Oct 2016 17:40:17 +0000 (-0700)
Subject: Add test for memory read from invalid address.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=acb593160f2f7e22bfd6a480570f2c5094634165;p=riscv-tests.git

Add test for memory read from invalid address.
---

diff --git a/debug/gdbserver.py b/debug/gdbserver.py
index 81aafa3..91c385f 100755
--- a/debug/gdbserver.py
+++ b/debug/gdbserver.py
@@ -293,6 +293,16 @@ class MemTest64(SimpleMemoryTest):
     def test(self):
         self.access_test(8, 'long long')
 
+class MemTestReadInvalid(SimpleMemoryTest):
+    def test(self):
+        # This test relies on 'gdb_report_data_abort enable' being executed in
+        # the openocd.cfg file.
+        try:
+            self.gdb.p("*((int*)0xdeadbeef)")
+            assert False, "Access should have failed."
+        except testlib.CannotAccess as e:
+            assertEqual(e.address, 0xdeadbeef)
+
 class MemTestBlock(GdbTest):
     def test(self):
         length = 1024
diff --git a/debug/targets/freedom-e300/openocd.cfg b/debug/targets/freedom-e300/openocd.cfg
index d448989..0596b15 100644
--- a/debug/targets/freedom-e300/openocd.cfg
+++ b/debug/targets/freedom-e300/openocd.cfg
@@ -8,6 +8,8 @@ jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10e31913
 set _TARGETNAME $_CHIPNAME.cpu
 target create $_TARGETNAME riscv -chain-position $_TARGETNAME
 
+gdb_report_data_abort enable
+
 init
 
 halt