From: Patrick Urban <patrick.urban@web.de>
Date: Fri, 24 Sep 2021 19:50:26 +0000 (+0200)
Subject: Allow initial blocks to be disabled during tests
X-Git-Tag: yosys-0.12~27
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=acb993b27b7027112bf10796efbf2886815f8630;p=yosys.git

Allow initial blocks to be disabled during tests

Wrap initial blocks with a NO_INIT so that tests for archs without register initialization feature don't fail.
---

diff --git a/tests/arch/common/adffs.v b/tests/arch/common/adffs.v
index 576bd81a6..966e7c2b8 100644
--- a/tests/arch/common/adffs.v
+++ b/tests/arch/common/adffs.v
@@ -1,7 +1,9 @@
 module adff( input d, clk, clr, output reg q );
+`ifndef NO_INIT
     initial begin
         q = 0;
     end
+`endif
 	  always @( posedge clk, posedge clr )
       if ( clr )
         q <= 1'b0;
@@ -10,9 +12,11 @@ module adff( input d, clk, clr, output reg q );
 endmodule
 
 module adffn( input d, clk, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
 	  always @( posedge clk, negedge clr )
 		  if ( !clr )
 			  q <= 1'b0;
@@ -21,9 +25,11 @@ module adffn( input d, clk, clr, output reg q );
 endmodule
 
 module dffs( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
     always @( posedge clk )
       if ( pre )
         q <= 1'b1;
@@ -32,9 +38,11 @@ module dffs( input d, clk, pre, clr, output reg q );
 endmodule
 
 module ndffnr( input d, clk, pre, clr, output reg q );
+`ifndef NO_INIT
     initial begin
       q = 0;
     end
+`endif
     always @( negedge clk )
       if ( !clr )
         q <= 1'b0;
diff --git a/tests/arch/common/dffs.v b/tests/arch/common/dffs.v
index 636252d16..0c607af50 100644
--- a/tests/arch/common/dffs.v
+++ b/tests/arch/common/dffs.v
@@ -4,9 +4,11 @@ module dff ( input d, clk, output reg q );
 endmodule
 
 module dffe( input d, clk, en, output reg q );
+`ifndef NO_INIT
     initial begin
         q = 0;
     end
+`endif
 	  always @( posedge clk )
         if ( en )
               q <= d;
diff --git a/tests/arch/common/shifter.v b/tests/arch/common/shifter.v
index 3030608ab..06e63c9af 100644
--- a/tests/arch/common/shifter.v
+++ b/tests/arch/common/shifter.v
@@ -1,7 +1,13 @@
 module top(out, clk, in);
     output [7:0] out;
     input signed clk, in;
-    reg signed [7:0] out = 0;
+    reg signed [7:0] out;
+
+`ifndef NO_INIT
+    initial begin
+        out = 0;
+    end
+`endif
 
     always @(posedge clk)
 	begin
diff --git a/tests/arch/gatemate/adffs.ys b/tests/arch/gatemate/adffs.ys
index 7bba699f6..3f9401d68 100644
--- a/tests/arch/gatemate/adffs.ys
+++ b/tests/arch/gatemate/adffs.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/adffs.v
+read_verilog -D NO_INIT ../common/adffs.v
 design -save read
 
 hierarchy -top adff
diff --git a/tests/arch/gatemate/dffs.ys b/tests/arch/gatemate/dffs.ys
index 0a3944e50..022322419 100644
--- a/tests/arch/gatemate/dffs.ys
+++ b/tests/arch/gatemate/dffs.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/dffs.v
+read_verilog -D NO_INIT ../common/dffs.v
 design -save read
 
 hierarchy -top dff
diff --git a/tests/arch/gatemate/shifter.ys b/tests/arch/gatemate/shifter.ys
index 03df36ebc..0006a298a 100644
--- a/tests/arch/gatemate/shifter.ys
+++ b/tests/arch/gatemate/shifter.ys
@@ -1,4 +1,4 @@
-read_verilog ../common/shifter.v
+read_verilog -D NO_INIT ../common/shifter.v
 hierarchy -top top
 proc
 flatten