From: Florent Kermarrec Date: Thu, 14 Aug 2014 14:32:29 +0000 (+0200) Subject: k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim) X-Git-Tag: 24jan2021_ls180~2662 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=acbba37f5f2e88f51bd15d0e66e30f926f9fb726;p=litex.git k7ddrphy: set bitslip to 0 on ISERDESE2 (needed at least for sim) --- diff --git a/misoclib/sdramphy/k7ddrphy.py b/misoclib/sdramphy/k7ddrphy.py index cd071960..83171224 100644 --- a/misoclib/sdramphy/k7ddrphy.py +++ b/misoclib/sdramphy/k7ddrphy.py @@ -185,6 +185,7 @@ class K7DDRPHY(Module): i_CE1=1, i_RST=ResetSignal(), i_CLK=ClockSignal("sys4x"), i_CLKB=~ClockSignal("sys4x"), i_CLKDIV=ClockSignal(), + i_BITSLIP=0, o_Q8=self.dfi.phases[0].rddata[i], o_Q7=self.dfi.phases[0].rddata[d+i], o_Q6=self.dfi.phases[1].rddata[i], o_Q5=self.dfi.phases[1].rddata[d+i], o_Q4=self.dfi.phases[2].rddata[i], o_Q3=self.dfi.phases[2].rddata[d+i],