From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 13 May 2021 21:12:33 +0000 (+0100)
Subject: minor rework of wb_get, make generic
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=acd1da7b3604e36deba6be59226eeeaacd0ccf60;p=soc.git

minor rework of wb_get, make generic
---

diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py
index 9c1d83bc..aa3087c6 100644
--- a/src/soc/experiment/test/test_ldst_pi.py
+++ b/src/soc/experiment/test/test_ldst_pi.py
@@ -28,38 +28,16 @@ from nmigen.compat.sim import run_simulation
 
 stop = False
 
-def wb_get(wb):
+def b(x): # byte-reverse function
+    return int.from_bytes(x.to_bytes(8, byteorder='little'),
+                          byteorder='big', signed=False)
+
+def wb_get(wb, mem):
     """simulator process for getting memory load requests
     """
 
     global stop
 
-    def b(x):
-        return int.from_bytes(x.to_bytes(8, byteorder='little'),
-                              byteorder='big', signed=False)
-
-    mem = {0x10000:    # PARTITION_TABLE_2
-                       # PATB_GR=1 PRTB=0x1000 PRTS=0xb
-           b(0x800000000100000b),
-
-           0x30000:     # RADIX_ROOT_PTE
-                        # V = 1 L = 0 NLB = 0x400 NLS = 9
-           b(0x8000000000040009),
-
-           0x40000:     # RADIX_SECOND_LEVEL
-                        # 	   V = 1 L = 1 SW = 0 RPN = 0
-                           # R = 1 C = 1 ATT = 0 EAA 0x7
-           b(0xc000000000000187),
-
-          0x1000000:   # PROCESS_TABLE_3
-                       # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
-           b(0x40000000000300ad),
-
-         # data to return
-          0x1000: 0xdeadbeef01234567,
-          0x1008: 0xfeedf00ff001a5a5
-          }
-
     while not stop:
         while True: # wait for dc_valid
             if stop:
@@ -203,13 +181,37 @@ def test_mmu():
     comb += l_in.eq(ldst.m_out)
     comb += ldst.m_in.eq(l_out)
 
+    # virtual "memory" to use for this test
+
+    mem = {0x10000:    # PARTITION_TABLE_2
+                       # PATB_GR=1 PRTB=0x1000 PRTS=0xb
+           b(0x800000000100000b),
+
+           0x30000:     # RADIX_ROOT_PTE
+                        # V = 1 L = 0 NLB = 0x400 NLS = 9
+           b(0x8000000000040009),
+
+           0x40000:     # RADIX_SECOND_LEVEL
+                        # 	   V = 1 L = 1 SW = 0 RPN = 0
+                           # R = 1 C = 1 ATT = 0 EAA 0x7
+           b(0xc000000000000183),
+
+          0x1000000:   # PROCESS_TABLE_3
+                       # RTS1 = 0x2 RPDB = 0x300 RTS2 = 0x5 RPDS = 13
+           b(0x40000000000300ad),
+
+         # data to return
+          0x1000: 0xdeadbeef01234567,
+          0x1008: 0xfeedf00ff001a5a5
+          }
+
 
     # nmigen Simulation
     sim = Simulator(m)
     sim.add_clock(1e-6)
 
     sim.add_sync_process(wrap(ldst_sim(m)))
-    sim.add_sync_process(wrap(wb_get(cmpi.wb_bus())))
+    sim.add_sync_process(wrap(wb_get(cmpi.wb_bus(), mem)))
     with sim.write_vcd('test_ldst_pi.vcd'):
         sim.run()