From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 2 Jun 2020 18:20:52 +0000 (+0100)
Subject: add regspecmap function to PowerDecode2
X-Git-Tag: div_pipeline~645
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=acd9406d4d7ec8abb2edd6f52b5b0b7f1ee145e3;p=soc.git

add regspecmap function to PowerDecode2
---

diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py
index 40071b34..a3d8d9b6 100644
--- a/src/soc/decoder/power_decoder2.py
+++ b/src/soc/decoder/power_decoder2.py
@@ -9,6 +9,7 @@ from nmigen.cli import rtlil
 from nmutil.iocontrol import RecordObject
 from nmutil.extend import exts
 
+from soc.decoder.power_regspec_map import regspec_decode
 from soc.decoder.power_decoder import create_pdecode
 from soc.decoder.power_enums import (InternalOp, CryIn, Function,
                                      CRInSel, CROutSel,
@@ -593,6 +594,13 @@ class PowerDecode2(Elaboratable):
 
         return m
 
+    def regspecmap(self, regfile, regname):
+        """regspecmap: provides PowerDecode2 with an encoding relationship
+        to Function Unit port regfiles (read-enable, read regnum, write regnum)
+        regfile and regname arguments are fields 1 and 2 from a given regspec.
+        """
+        return regspec_decode(self, regfile, regname)
+
 
 if __name__ == '__main__':
     pdecode = create_pdecode()