From: Jim Wilson <wilson@gcc.gnu.org>
Date: Mon, 8 Jul 2019 10:47:42 +0000 (-0700)
Subject: RISC-V: Fix splitter for 32-bit AND on 64-bit target.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ace4317affd3068cc01c06f0928e119f1559519c;p=gcc.git

RISC-V: Fix splitter for 32-bit AND on 64-bit target.

Fixes github.com/riscv/riscv-gcc issue #161.  We were accidentally using
BITS_PER_WORD to compute shift counts when we should have been using the
bitsize of the operand modes.  This was wrong when we had an SImode shift
and a 64-bit target.

	Andrew Waterman  <andrew@sifive.com>
	gcc/
	* config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
	bitsize	instead of BITS_PER_WORD.
	gcc/testsuite/
	* gcc.target/riscv/shift-shift-2.c: Add one more test.

From-SVN: r273230
---

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 31ad4e5208e..6429407bc4b 100644
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,10 @@
+2019-07-08  Andrew Waterman  <andrew@sifive.com>
+	    Jim Wilson  <jimw@sifive.com>
+
+	* config/riscv/riscv.md (lshrsi3_zero_extend_3+1): Use operands[1]
+	bitsize	instead of BITS_PER_WORD.
+	gcc/testsuite/
+
 2019-07-08  Martin Liska  <mliska@suse.cz>
 
 	* collect2.c (defined): Revert to before r254460.
diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index 0f4626656d6..78260fcf6fd 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1776,10 +1776,11 @@
   (set (match_dup 0)
        (lshiftrt:GPR (match_dup 0) (match_dup 2)))]
 {
-  operands[2] = GEN_INT (BITS_PER_WORD
+  /* Op2 is a VOIDmode constant, so get the mode size from op1.  */
+  operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1]))
 			 - exact_log2 (INTVAL (operands[2]) + 1));
 })
-  
+
 ;; Handle AND with 0xF...F0...0 where there are 32 to 63 zeros.  This can be
 ;; split into two shifts.  Otherwise it requires 3 instructions: li, sll, and.
 (define_split
diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog
index 61150ea17ba..56f2f2c5964 100644
--- a/gcc/testsuite/ChangeLog
+++ b/gcc/testsuite/ChangeLog
@@ -1,3 +1,7 @@
+2019-07-08  Jim Wilson  <jimw@sifive.com>
+
+	* gcc.target/riscv/shift-shift-2.c: Add one more test.
+
 2019-07-08  Paolo Carlini  <paolo.carlini@oracle.com>
 
 	PR c++/65143
diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
index 3f07e7776e7..10a5bb728be 100644
--- a/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
+++ b/gcc/testsuite/gcc.target/riscv/shift-shift-2.c
@@ -25,5 +25,17 @@ sub4 (unsigned long i)
 {
   return (i << 52) >> 52;
 }
-/* { dg-final { scan-assembler-times "slli" 4 } } */
-/* { dg-final { scan-assembler-times "srli" 4 } } */
+
+unsigned int
+sub5 (unsigned int i)
+{
+  unsigned int j;
+  j = i >> 24;
+  j = j * (1 << 24);
+  j = i - j;
+  return j;
+}
+/* { dg-final { scan-assembler-times "slli" 5 } } */
+/* { dg-final { scan-assembler-times "srli" 5 } } */
+/* { dg-final { scan-assembler-times "slliw" 1 } } */
+/* { dg-final { scan-assembler-times "srliw" 1 } } */