From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 5 Jul 2022 17:19:29 +0000 (+0100)
Subject: add note about bug #884 new reg vector naming convention
X-Git-Tag: sv_maxu_works-initial~299
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=acf232eef710e74263728e3ba2f93bf0dfc3e5cc;p=openpower-isa.git

add note about bug #884 new reg vector naming convention
---

diff --git a/src/openpower/sv/trans/svp64.py b/src/openpower/sv/trans/svp64.py
index c7b01721..9efcf1c9 100644
--- a/src/openpower/sv/trans/svp64.py
+++ b/src/openpower/sv/trans/svp64.py
@@ -468,6 +468,8 @@ def decode_ffirst(encoding):
 
 def decode_reg(field):
     # decode the field number. "5.v" or "3.s" or "9"
+    # and now also "*0", and "*%0".  note: *NOT* to add "*%rNNN" etc.
+    # https://bugs.libre-soc.org/show_bug.cgi?id=884#c0
     field = field.split(".")
     regmode = 'scalar'  # default
     if len(field) == 2: