From: Cui Jin <cuijin7@huawei.com>
Date: Tue, 22 Dec 2020 08:46:46 +0000 (+0800)
Subject: arch-riscv: fix MIE csr register setting bugs
X-Git-Tag: develop-gem5-snapshot~329
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=acfb233685a69078ef9c04829815436b687beae8;p=gem5.git

arch-riscv: fix MIE csr register setting bugs

Any changes on xIE bits changes should trigger the updating
of CSR register. The old condition is wrongly reversed.

The fix is verified in FS.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-855

Change-Id: Ia2c6d3fbfd24d7f9d23f7cfa6f25f893544f4157
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/38578
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---

diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 72f7dc1d2..b95af7623 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -383,9 +383,9 @@ def template CSRExecute {{
                             xc->setMiscReg(MISCREG_FRM, bits(data, 7, 5));
                             break;
                           case CSR_MIP: case CSR_MIE:
-                            if (oldinterrupt.mei == newinterrupt.mei &&
-                                oldinterrupt.mti == newinterrupt.mti &&
-                                oldinterrupt.msi == newinterrupt.msi) {
+                            if (oldinterrupt.mei != newinterrupt.mei ||
+                                oldinterrupt.mti != newinterrupt.mti ||
+                                oldinterrupt.msi != newinterrupt.msi) {
                                 xc->setMiscReg(CSRData.at(csr).physIndex,data);
                             } else {
                                 std::string error = "Interrupt m bits are "