From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 5 Mar 2020 10:19:29 +0000 (+0100)
Subject: targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
X-Git-Tag: 24jan2021_ls180~597
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad11ff39ad7f392642b3b0a41f5048b27ad88935;p=litex.git

targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
---

diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py
index 5fe17147..ce7a13d9 100755
--- a/litex/boards/targets/versa_ecp5.py
+++ b/litex/boards/targets/versa_ecp5.py
@@ -72,7 +72,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCSDRAM):
-    def __init__(self, sys_clk_freq=int(75e6), toolchain="diamond", **kwargs):
+    def __init__(self, sys_clk_freq=int(75e6), toolchain="trellis", **kwargs):
         platform = versa_ecp5.Platform(toolchain=toolchain)
 
         # SoCSDRAM ---------------------------------------------------------------------------------