From: Dmitry Selyutin <ghostmansd@gmail.com>
Date: Sun, 18 Sep 2022 18:56:22 +0000 (+0300)
Subject: power_insn: fix CR ops classes naming
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad14ae60ceeed2f008ecc729973508d961af5091;p=openpower-isa.git

power_insn: fix CR ops classes naming
---

diff --git a/src/openpower/decoder/power_insn.py b/src/openpower/decoder/power_insn.py
index 05c64856..b859c822 100644
--- a/src/openpower/decoder/power_insn.py
+++ b/src/openpower/decoder/power_insn.py
@@ -1643,7 +1643,7 @@ class CROpSMRRM(DZBaseRM, SZBaseRM, CROpBaseRM):
         yield from super().specifiers(record=record)
 
 
-class CROpFailFirst3RM(ZZBaseRM, CROpBaseRM):
+class CROpFF3RM(ZZBaseRM, CROpBaseRM):
     """cr_op: ffirst 3-bit mode"""
     VLI: BaseRM[20]
     inv: BaseRM[21]
@@ -1652,7 +1652,7 @@ class CROpFailFirst3RM(ZZBaseRM, CROpBaseRM):
     dz: BaseRM[22]
 
 
-class CROpFailFirst5RM(DZBaseRM, SZBaseRM, CROpBaseRM):
+class CROpFF5RM(DZBaseRM, SZBaseRM, CROpBaseRM):
     """cr_op: ffirst 5-bit mode"""
     VLI: BaseRM[20]
     inv: BaseRM[21]
@@ -1666,8 +1666,8 @@ class CROpFailFirst5RM(DZBaseRM, SZBaseRM, CROpBaseRM):
 class CROpRM(CROpBaseRM):
     simple: CROpSimpleRM
     smr: CROpSMRRM
-    ff3: CROpFailFirst3RM
-    ff5: CROpFailFirst5RM
+    ff3: CROpFF3RM
+    ff5: CROpFF5RM
 
 
 # ********************