From: Eric Anholt <eric@anholt.net>
Date: Fri, 3 Dec 2010 20:38:08 +0000 (-0800)
Subject: i965: Fix gen6 interpolation setup for 16-wide.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad29e798504fcaf23ac3f2656bcfb8d8e19ca183;p=mesa.git

i965: Fix gen6 interpolation setup for 16-wide.

In the SF and brw_fs.cpp fixes to set up interpolation sanely on gen6,
the setup for 16-wide interpolation was left behind.  This brings
relative sanity to that path too.
---

diff --git a/src/mesa/drivers/dri/i965/brw_wm_pass2.c b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
index 7b25dc11f10..8c2b9e7020b 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_pass2.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_pass2.c
@@ -69,6 +69,8 @@ static void prealloc_reg(struct brw_wm_compile *c,
  */
 static void init_registers( struct brw_wm_compile *c )
 {
+   struct brw_context *brw = c->func.brw;
+   struct intel_context *intel = &brw->intel;
    GLuint nr_interp_regs = 0;
    GLuint i = 0;
    GLuint j;
@@ -82,24 +84,33 @@ static void init_registers( struct brw_wm_compile *c )
    for (j = 0; j < c->nr_creg; j++) 
       prealloc_reg(c, &c->creg[j], i++);
 
-   for (j = 0; j < VERT_RESULT_MAX; j++) {
-      if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) {
-	 int fp_index;
-
-	 if (j >= VERT_RESULT_VAR0)
-	    fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
-	 else if (j <= VERT_RESULT_TEX7)
-	    fp_index = j;
-	 else
-	    fp_index = -1;
-
-	 nr_interp_regs++;
-	 if (fp_index >= 0)
-	    prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
+   if (intel->gen >= 6) {
+      for (unsigned int j = 0; j < FRAG_ATTRIB_MAX; j++) {
+	 if (brw->fragment_program->Base.InputsRead & BITFIELD64_BIT(j)) {
+	    nr_interp_regs++;
+	    prealloc_reg(c, &c->payload.input_interp[j], i++);
+	 }
+      }
+   } else {
+      for (j = 0; j < VERT_RESULT_MAX; j++) {
+	 if (c->key.vp_outputs_written & BITFIELD64_BIT(j)) {
+	    int fp_index;
+
+	    if (j >= VERT_RESULT_VAR0)
+	       fp_index = j - (VERT_RESULT_VAR0 - FRAG_ATTRIB_VAR0);
+	    else if (j <= VERT_RESULT_TEX7)
+	       fp_index = j;
+	    else
+	       fp_index = -1;
+
+	    nr_interp_regs++;
+	    if (fp_index >= 0)
+	       prealloc_reg(c, &c->payload.input_interp[fp_index], i++);
+	 }
       }
+      assert(nr_interp_regs >= 1);
    }
 
-   assert(nr_interp_regs >= 1);
 
    c->prog_data.first_curbe_grf = ALIGN(c->nr_payload_regs, 2);
    c->prog_data.urb_read_length = nr_interp_regs * 2;