From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 11 Jul 2019 02:05:53 +0000 (-0700)
Subject: Another typo
X-Git-Tag: working-ls180~881^2^2~269
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad35b509de55df1ab5c6a360adec1e3777ba2410;p=yosys.git

Another typo
---

diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 96cbb1e04..91cfbc4c4 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -68,7 +68,7 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   );
   \$__ABC_FF_ abc_dff (.D(\$nextQ ), .Q(\$currQ ));
   generate
-    if (IS_PRE_INVERTED)
+    if (IS_CLR_INVERTED)
       \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(\$currQ ), .B(1'b0), .S(CLR), .Y(Q));
     else
       \$__ABC_FD_ASYNC_MUX abc_async_mux (.A(1'b0), .B(\$currQ ), .S(CLR), .Y(Q));