From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 21 Jun 2019 02:31:22 +0000 (-0700)
Subject: Fix different abc9 test
X-Git-Tag: working-ls180~1237^2~76
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad36eb24c05b578ec8610c9f199280aacefebe54;p=yosys.git

Fix different abc9 test
---

diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc
index f0a9ccdb9..55a95d835 100644
--- a/backends/aiger/xaiger.cc
+++ b/backends/aiger/xaiger.cc
@@ -406,13 +406,14 @@ struct XAigerWriter
 		}
 
 		for (auto bit : input_bits) {
+			if (!output_bits.count(bit))
+				continue;
 			RTLIL::Wire *wire = bit.wire;
 			// If encountering an inout port, or a keep-ed wire, then create a new wire
 			// with $inout.out suffix, make it a PO driven by the existing inout, and
 			// inherit existing inout's drivers
-			if ((wire->port_input && wire->port_output && output_bits.count(bit) && !undriven_bits.count(bit))
+			if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
 					|| wire->attributes.count("\\keep")) {
-				log_assert(output_bits.count(bit));
 				RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
 				RTLIL::Wire *new_wire = module->wire(wire_name);
 				if (!new_wire)