From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 7 Sep 2021 13:40:39 +0000 (+0100)
Subject: whitespace, add bug ref number to test API
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad3ef62fb06fd23edc51c2b5d33e0d82fe3597ec;p=soc.git

whitespace, add bug ref number to test API
---

diff --git a/src/soc/simple/test/test_core.py b/src/soc/simple/test/test_core.py
index a3554502..836ed5bd 100644
--- a/src/soc/simple/test/test_core.py
+++ b/src/soc/simple/test/test_core.py
@@ -3,7 +3,9 @@
 related bugs:
 
  * https://bugs.libre-soc.org/show_bug.cgi?id=363
+ * https://bugs.libre-soc.org/show_bug.cgi?id=686
 """
+
 from nmigen import Module, Signal, Cat
 from nmigen.back.pysim import Simulator, Delay, Settle
 from nmutil.formaltest import FHDLTestCase
@@ -40,6 +42,7 @@ from openpower.util import spr_to_fast_reg
 # list of SPRs that are controlled and managed by the MMU
 mmu_sprs = ["PRTBL", "DSISR", "DAR", "PIDR"]
 
+
 def set_mmu_spr(name, i, val, core): #important keep pep8 formatting
         fsm = core.fus.get_fu("mmu0").alu
         yield fsm.mmu.l_in.mtspr.eq(1)
@@ -49,6 +52,7 @@ def set_mmu_spr(name, i, val, core): #important keep pep8 formatting
         yield fsm.mmu.l_in.mtspr.eq(0)
         print("mmu_spr was updated")
 
+
 def setup_regs(pdecode2, core, test):
 
     # set up INT regfile, "direct" write (bypass rd/write ports)