From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 19 Apr 2021 17:55:50 +0000 (+0100)
Subject: give independent names to spblock512w64b8ws
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad4fb0e1da6662768da85bb2941a883d4c0bb69e;p=soc.git

give independent names to spblock512w64b8ws
---

diff --git a/src/soc/bus/SPBlock512W64B8W.py b/src/soc/bus/SPBlock512W64B8W.py
index d00aa532..70ed531b 100644
--- a/src/soc/bus/SPBlock512W64B8W.py
+++ b/src/soc/bus/SPBlock512W64B8W.py
@@ -13,6 +13,10 @@ class SPBlock512W64B8W(Elaboratable):
     """
 
     def __init__(self, bus=None, features=None, name=None):
+        if name:
+            self.idx = int(name.split("_")[-1])
+        else:
+            self.idx = 0
         self.enable = Signal(reset=1) # enable signal, defaults to 1
         if features is None:
             features = frozenset()
@@ -44,8 +48,10 @@ class SPBlock512W64B8W(Elaboratable):
 
         # create Chips4Makers 4k SRAM cell here, mark it as "black box"
         # for coriolis2 to pick up
-        sram = Instance("spblock512w64b8w", i_a=a, o_q=q, i_d=d,
-                                            i_we=we, i_clk=ClockSignal())
+        idx = self.idx
+        sram = Instance("spblock512w64b8w_%d" % idx, i_a=a, o_q=q,
+                                                     i_d=d, i_we=we,
+                                                     i_clk=ClockSignal())
         m.submodules.spb = sram
         # has to be added to the actual module rather than the instance
         # sram.attrs['blackbox'] = 1