From: Sandipan Das <sandipan@linux.vnet.ibm.com>
Date: Thu, 7 Jun 2018 14:33:01 +0000 (+0530)
Subject: arch-power: Add branch target address register instructions
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad502b3d7bf7835440c715ff7d14d668988c1ae1;p=gem5.git

arch-power: Add branch target address register instructions

This adds the definition of the Target Address Register (TAR)
and the following instructions that are associated with it:
  * Move To Target Address Register (mttar)
  * Move From Target Address Register (mftar)
  * Branch Conditional to Branch Target Address Register (bctar[l])

Change-Id: I5130a22040e30a05e963b1cc8d38abbed9a49edb
Signed-off-by: Sandipan Das <sandipan@linux.vnet.ibm.com>
---

diff --git a/src/arch/power/isa/decoder.isa b/src/arch/power/isa/decoder.isa
index 69048ba8c..a42f63da8 100644
--- a/src/arch/power/isa/decoder.isa
+++ b/src/arch/power/isa/decoder.isa
@@ -56,6 +56,7 @@ decode PO default Unknown::unknown() {
         format BranchRegCondOp {
             16: bclr({{ NIA = LR & -4ULL; }}, true, [ IsReturn ]);
             528: bcctr({{ NIA = CTR & -4ULL; }});
+            560: bctar({{ NIA = TAR & -4ULL; }}, true);
         }
 
         // Condition register manipulation instructions.
@@ -703,11 +704,13 @@ decode PO default Unknown::unknown() {
                 0x20: mfxer({{ Rt = XER; }});
                 0x100: mflr({{ Rt = LR; }});
                 0x120: mfctr({{ Rt = CTR; }});
+                0x32f: mftar({{ Rt = TAR; }});
             }
             467: decode SPR {
                 0x20: mtxer({{ XER = Rs; }});
                 0x100: mtlr({{ LR = Rs; }});
                 0x120: mtctr({{ CTR = Rs; }});
+                0x32f: mttar({{ TAR = Rs; }});
             }
         }
 
diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index db440805e..e0788e101 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -63,9 +63,10 @@ def operands {{
 
     # Control registers
     'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
+    'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
     'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
     'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
-    'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
+    'TAR': ('IntReg', 'ud', 'INTREG_TAR', 'IsInteger', 9),
 
     # Setting as IntReg so things are stored as an integer, not double
     'FPSCR': ('IntReg', 'uw', 'INTREG_FPSCR', 'IsFloating', 9),
diff --git a/src/arch/power/registers.hh b/src/arch/power/registers.hh
index a6d28a80e..a6ec90ce4 100644
--- a/src/arch/power/registers.hh
+++ b/src/arch/power/registers.hh
@@ -62,9 +62,9 @@ constexpr bool VecPredRegHasPackedRepr = ::DummyVecPredRegHasPackedRepr;
 // Constants Related to the number of registers
 const int NumIntArchRegs = 32;
 
-// CR, XER, LR, CTR, FPSCR, RSV, RSV-LEN, RSV-ADDR
+// CR, XER, LR, CTR, TAR, FPSCR, RSV, RSV-LEN, RSV-ADDR
 // and zero register, which doesn't actually exist but needs a number
-const int NumIntSpecialRegs = 9;
+const int NumIntSpecialRegs = 10;
 const int NumFloatArchRegs = 32;
 const int NumFloatSpecialRegs = 0;
 const int NumInternalProcRegs = 0;
@@ -100,6 +100,7 @@ enum MiscIntRegNums {
     INTREG_XER,
     INTREG_LR,
     INTREG_CTR,
+    INTREG_TAR,
     INTREG_FPSCR,
     INTREG_RSV,
     INTREG_RSV_LEN,