From: lkcl <lkcl@web>
Date: Mon, 16 Aug 2021 15:50:26 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: DRAFT_SVP64_0_1~424
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad5af8fed14dffba339eaad1e80c4a9e834aa11a;p=libreriscv.git

---

diff --git a/openpower/sv/branches.mdwn b/openpower/sv/branches.mdwn
index 5bf1f0fc3..5ded5ded2 100644
--- a/openpower/sv/branches.mdwn
+++ b/openpower/sv/branches.mdwn
@@ -79,7 +79,9 @@ Vector Processing. The reason is to have strictly-defined guaranteed
 behaviour*)
 
 In Vertical-First Mode, the `ALL` bit still applies, but to the elements
-that are executed up to the Hint length, in parallel batches. See
+that are executed up to the Hint length, in parallel batches. Contrast
+this with Horizontal-First Mode which tests elements from
+`0..VL-1`, Vertical-First tests elements `srcstep..MIN(srcstep+VFHint,VL-1)` See
 [[sv/setvl]] for the definition of Vertical-First Hint.
 
 Predication in both INT and CR modes may be applied to `sv.bc` and other