From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 17 Jan 2020 23:38:26 +0000 (-0800)
Subject: ice40_dsp: add test
X-Git-Tag: working-ls180~863^2~6
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad6c49fff12e27d99c1fc15850857e5129dd76ee;p=yosys.git

ice40_dsp: add test
---

diff --git a/tests/arch/ice40/ice40_dsp.ys b/tests/arch/ice40/ice40_dsp.ys
new file mode 100644
index 000000000..250273859
--- /dev/null
+++ b/tests/arch/ice40/ice40_dsp.ys
@@ -0,0 +1,11 @@
+read_verilog <<EOT
+module top(input [15:0] a, b, output [31:0] o1, o2, o5);
+SB_MAC16 m1 (.A(a), .B(16'd1234), .O(o1));
+assign o2 = a * 16'd0;
+wire [31:0] o3, o4;
+SB_MAC16 m2 (.A(a), .B(b), .O(o3));
+assign o4 = a * b;
+SB_MAC16 m3 (.A(a), .B(b), .O(o5));
+endmodule
+EOT
+ice40_dsp