From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 15 Feb 2022 00:41:12 +0000 (+0000)
Subject: FLGA_TARGET=verilator not uppercase
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad6fb148968986d0c1180c3e6665113ece14e9c0;p=ls2.git

FLGA_TARGET=verilator not uppercase
---

diff --git a/Makefile b/Makefile
index 7baa465..fcb8127 100644
--- a/Makefile
+++ b/Makefile
@@ -39,7 +39,7 @@ SIM_MAIN_BRAM=false
 #SIM_MAIN_BRAM=false
 SIM_BRAM_CHAINBOOT=6291456 # 0x600000
 
-FPGA_TARGET ?= VERILATOR
+FPGA_TARGET ?= verilator
 
 ifeq ($(FPGA_TARGET), verilator)
 RESET_LOW=true