From: lkcl <lkcl@web>
Date: Sat, 29 Oct 2022 22:56:25 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~25
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad7e6a0b89e30603f1f429e37e0358b9a7271e7f;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls003.mdwn b/openpower/sv/rfc/ls003.mdwn
index d2ce0380e..dfc546291 100644
--- a/openpower/sv/rfc/ls003.mdwn
+++ b/openpower/sv/rfc/ls003.mdwn
@@ -248,6 +248,7 @@ Examples:
 # ((r0 << 64) + r2) % r1, store in r2
 divmod2du r4, r0, r1, r2
 ```
+\newpage{}
 
 # Double-Shift Left Doubleword
 
@@ -286,6 +287,8 @@ the overflow flag is raised in CR0.*
 *Programmer's note:
 similar to maddedu and divmod2du, dsld can be chained (using RC).*
 
+\newpage{}
+
 # Double-Shift Right Doubleword
 
 `dsrd RT,RA,RB,RC`
@@ -296,7 +299,7 @@ similar to maddedu and divmod2du, dsld can be chained (using RC).*
 
 Pseudo-code:
 
-    n <- (RB)[58:63]                        # Take lower 6-bits of RB for shift
+    n <- (RB)[58:63]                        # Take lower 6-bits for shift
     v <- ROTL64((RA), 64-n)                 # Rotate RA 64-bit left by 64-n bits
     mask <- MASK(n, 63)                     # 0's mask, set mask[n:63] to 1' 
     RT <- (v[0:63] & mask) | ((RC) & ¬mask) # 
@@ -309,7 +312,6 @@ Special Registers Altered:
 
     CR0                    (if Rc=1)
 
-
 \newpage{}
 
 # VA2-Form