From: Alyssa Rosenzweig Date: Fri, 2 Aug 2019 15:46:44 +0000 (-0700) Subject: pan/midgard: Promote all 16 uniforms X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad864a0bbbe1ff5b99d0eb4f9bbb57acb13bf6a2;p=mesa.git pan/midgard: Promote all 16 uniforms Now that register spilling is in place, this is reasonable. It turns out for some shaders, it's actually better to cap at 8 work registers and extra >8 uniform reigsters and tolerate the spilling, since the extra resulting threads make up for the spillage. So incidentally, the shader that spills here is in -bterrain, which jumps from 19fps to 21fps as a result of this change. total instructions in shared programs: 3513 -> 3448 (-1.85%) instructions in affected programs: 776 -> 711 (-8.38%) helped: 20 HURT: 0 helped stats (abs) min: 1 max: 8 x̄: 3.25 x̃: 2 helped stats (rel) min: 3.57% max: 16.00% x̄: 8.37% x̃: 7.19% 95% mean confidence interval for instructions value: -4.28 -2.22 95% mean confidence interval for instructions %-change: -10.02% -6.73% Instructions are helped. total bundles in shared programs: 2067 -> 2024 (-2.08%) bundles in affected programs: 515 -> 472 (-8.35%) helped: 19 HURT: 1 helped stats (abs) min: 1 max: 6 x̄: 2.37 x̃: 2 helped stats (rel) min: 2.13% max: 17.86% x̄: 10.19% x̃: 11.11% HURT stats (abs) min: 2 max: 2 x̄: 2.00 x̃: 2 HURT stats (rel) min: 3.23% max: 3.23% x̄: 3.23% x̃: 3.23% 95% mean confidence interval for bundles value: -3.01 -1.29 95% mean confidence interval for bundles %-change: -12.13% -6.91% Bundles are helped. total quadwords in shared programs: 3468 -> 3426 (-1.21%) quadwords in affected programs: 764 -> 722 (-5.50%) helped: 19 HURT: 1 helped stats (abs) min: 1 max: 5 x̄: 2.26 x̃: 2 helped stats (rel) min: 1.41% max: 12.50% x̄: 6.76% x̃: 7.14% HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1 HURT stats (rel) min: 1.08% max: 1.08% x̄: 1.08% x̃: 1.08% 95% mean confidence interval for quadwords value: -2.83 -1.37 95% mean confidence interval for quadwords %-change: -8.08% -4.65% Quadwords are helped. total registers in shared programs: 383 -> 360 (-6.01%) registers in affected programs: 112 -> 89 (-20.54%) helped: 19 HURT: 0 helped stats (abs) min: 1 max: 3 x̄: 1.21 x̃: 1 helped stats (rel) min: 12.50% max: 27.27% x̄: 20.63% x̃: 20.00% 95% mean confidence interval for registers value: -1.47 -0.95 95% mean confidence interval for registers %-change: -22.39% -18.87% Registers are helped. total threads in shared programs: 432 -> 451 (4.40%) threads in affected programs: 19 -> 38 (100.00%) helped: 11 HURT: 0 helped stats (abs) min: 1 max: 2 x̄: 1.73 x̃: 2 helped stats (rel) min: 100.00% max: 100.00% x̄: 100.00% x̃: 100.00% 95% mean confidence interval for threads value: 1.41 2.04 95% mean confidence interval for threads %-change: 100.00% 100.00% Threads are [helped]. total loops in shared programs: 4 -> 4 (0.00%) loops in affected programs: 0 -> 0 helped: 0 HURT: 0 total spills in shared programs: 0 -> 4 spills in affected programs: 0 -> 4 helped: 0 HURT: 2 total fills in shared programs: 0 -> 7 fills in affected programs: 0 -> 7 helped: 0 HURT: 2 Signed-off-by: Alyssa Rosenzweig --- diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h index 7a07bb847bf..da9e17f29c3 100644 --- a/src/panfrost/midgard/compiler.h +++ b/src/panfrost/midgard/compiler.h @@ -524,7 +524,7 @@ bool mir_has_multiple_writes(compiler_context *ctx, int src); void mir_create_pipeline_registers(compiler_context *ctx); void -midgard_promote_uniforms(compiler_context *ctx, unsigned pressure); +midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count); void emit_ubo_read( diff --git a/src/panfrost/midgard/midgard_schedule.c b/src/panfrost/midgard/midgard_schedule.c index 420c02e13f1..f59ef260d36 100644 --- a/src/panfrost/midgard/midgard_schedule.c +++ b/src/panfrost/midgard/midgard_schedule.c @@ -878,7 +878,7 @@ schedule_program(compiler_context *ctx) /* Number of 128-bit slots in memory we've spilled into */ unsigned spill_count = 0; - midgard_promote_uniforms(ctx, 8); + midgard_promote_uniforms(ctx, 16); mir_foreach_block(ctx, block) { midgard_pair_load_store(ctx, block); diff --git a/src/panfrost/midgard/mir_promote_uniforms.c b/src/panfrost/midgard/mir_promote_uniforms.c index 6c09fbe661e..e8da834b2fa 100644 --- a/src/panfrost/midgard/mir_promote_uniforms.c +++ b/src/panfrost/midgard/mir_promote_uniforms.c @@ -36,12 +36,8 @@ * spilling. If we spill anyway, I mean, it's a lose-lose at that point. */ void -midgard_promote_uniforms(compiler_context *ctx, unsigned register_pressure) +midgard_promote_uniforms(compiler_context *ctx, unsigned promoted_count) { - /* For our purposes, pressure is capped at the number of vec4 work - * registers, not live values which would consider spills */ - register_pressure = MAX2(register_pressure, 16); - mir_foreach_instr_global_safe(ctx, ins) { if (ins->type != TAG_LOAD_STORE_4) continue; if (!OP_IS_UBO_READ(ins->load_store.op)) continue; @@ -61,8 +57,7 @@ midgard_promote_uniforms(compiler_context *ctx, unsigned register_pressure) /* Check if it's a promotable range */ unsigned uniform_reg = 23 - address; - if (address > 16) continue; - if (register_pressure > uniform_reg) continue; + if (address >= promoted_count) continue; /* It is, great! Let's promote */