From: lkcl <lkcl@web>
Date: Sun, 19 Jun 2022 23:35:11 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad8a2f52ca2ad05128d552ad2bd9b5592a9dd712;p=libreriscv.git

---

diff --git a/openpower/sv/vector_ops.mdwn b/openpower/sv/vector_ops.mdwn
index 82efc4c3f..68e37fbe2 100644
--- a/openpower/sv/vector_ops.mdwn
+++ b/openpower/sv/vector_ops.mdwn
@@ -199,6 +199,8 @@ pseudocode:
                     setting_mode = True # back into "setting" mode
             i += 1
 
+<https://github.com/riscv-software-src/riscv-isa-sim/blob/master/riscv/insns/vmsbf_m.h>
+
 ## sifm
 
 The vector mask set-including-first instruction is similar to set-before-first, except it also includes the element with a set bit.