From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 18 Jul 2015 10:16:27 +0000 (+0200)
Subject: Fixed techmap processes error msg
X-Git-Tag: yosys-0.6~225
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad919ae4e3a86e6726adf8dd66ae5468397c9d27;p=yosys.git

Fixed techmap processes error msg
---

diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 63923a5cf..1fb19fc60 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -159,9 +159,10 @@ struct TechmapWorker
 	void techmap_module_worker(RTLIL::Design *design, RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::Module *tpl)
 	{
 		if (tpl->processes.size() != 0) {
-			log("Technology map yielded processes:\n");
+			log("Technology map yielded processes:");
 			for (auto &it : tpl->processes)
-				log("  %s",RTLIL::id2cstr(it.first));
+				log(" %s",RTLIL::id2cstr(it.first));
+			log("\n");
 			if (autoproc_mode) {
 				Pass::call_on_module(tpl->design, tpl, "proc");
 				log_assert(GetSize(tpl->processes) == 0);