From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Date: Fri, 18 Jan 2019 16:12:06 +0000 (+0000)
Subject: intel/genxml: add missing MI_PREDICATE compare operations
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ad99c1670abef58da5184361b7e51d08c65f8a86;p=mesa.git

intel/genxml: add missing MI_PREDICATE compare operations

Doesn't save us a great deal of lines but at least they get decoded in
aubinators.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
---

diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml
index 9ec311d6cc5..7043ab8995d 100644
--- a/src/intel/genxml/gen10.xml
+++ b/src/intel/genxml/gen10.xml
@@ -3047,6 +3047,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>
diff --git a/src/intel/genxml/gen11.xml b/src/intel/genxml/gen11.xml
index 6ab1f965650..3af80a6ed3d 100644
--- a/src/intel/genxml/gen11.xml
+++ b/src/intel/genxml/gen11.xml
@@ -3042,6 +3042,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>
diff --git a/src/intel/genxml/gen7.xml b/src/intel/genxml/gen7.xml
index 893c12b8af9..3c445757300 100644
--- a/src/intel/genxml/gen7.xml
+++ b/src/intel/genxml/gen7.xml
@@ -2051,6 +2051,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>
diff --git a/src/intel/genxml/gen75.xml b/src/intel/genxml/gen75.xml
index 009a123ad69..3df7dc29939 100644
--- a/src/intel/genxml/gen75.xml
+++ b/src/intel/genxml/gen75.xml
@@ -2462,6 +2462,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>
diff --git a/src/intel/genxml/gen8.xml b/src/intel/genxml/gen8.xml
index fd19b0c8b33..4d1488dae62 100644
--- a/src/intel/genxml/gen8.xml
+++ b/src/intel/genxml/gen8.xml
@@ -2690,6 +2690,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>
diff --git a/src/intel/genxml/gen9.xml b/src/intel/genxml/gen9.xml
index 706d398babb..3f02e866d0c 100644
--- a/src/intel/genxml/gen9.xml
+++ b/src/intel/genxml/gen9.xml
@@ -2973,6 +2973,8 @@
       <value name="XOR" value="3"/>
     </field>
     <field name="Compare Operation" start="0" end="1" type="uint" prefix="COMPARE">
+      <value name="TRUE" value="0"/>
+      <value name="FALSE" value="1"/>
       <value name="SRCS_EQUAL" value="2"/>
       <value name="DELTAS_EQUAL" value="3"/>
     </field>
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 2d94d85d141..cec4819ba4a 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -3568,7 +3568,6 @@ void genX(CmdDispatchIndirect)(
    }
 
    /* predicate = !predicate; */
-#define COMPARE_FALSE                           1
    anv_batch_emit(batch, GENX(MI_PREDICATE), mip) {
       mip.LoadOperation    = LOAD_LOADINV;
       mip.CombineOperation = COMBINE_OR;