From: Sebastien Bourdeauducq <sebastien@milkymist.org>
Date: Fri, 30 Nov 2012 16:07:32 +0000 (+0100)
Subject: pytholite: fix bit width of selection signal
X-Git-Tag: 24jan2021_ls180~2099^2~729
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=adb1565d7a4076039f5cde517a7134b4aa0ccd2f;p=litex.git

pytholite: fix bit width of selection signal
---

diff --git a/migen/pytholite/reg.py b/migen/pytholite/reg.py
index 32bb348c..5ec49c4a 100644
--- a/migen/pytholite/reg.py
+++ b/migen/pytholite/reg.py
@@ -40,7 +40,7 @@ class ImplRegister:
 	def finalize(self):
 		if self.finalized:
 			raise FinalizeError
-		self.sel = Signal(max=len(self.source_encoding)+2, name="pl_regsel_"+self.name)
+		self.sel = Signal(max=len(self.source_encoding)+1, name="pl_regsel_"+self.name)
 		self.finalized = True
 	
 	def get_fragment(self):