From: Tobias Platen <tplaten@posteo.de>
Date: Sat, 6 Nov 2021 14:14:47 +0000 (+0100)
Subject: update test_issuer_mmu.py testcase, add needed debug outputs
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=adb9b764763cf64e7c62ddabb356b7e6f8d48785;p=soc.git

update test_issuer_mmu.py testcase, add needed debug outputs
---

diff --git a/src/soc/experiment/compldst_multi.py b/src/soc/experiment/compldst_multi.py
index f94252f4..a160ad10 100644
--- a/src/soc/experiment/compldst_multi.py
+++ b/src/soc/experiment/compldst_multi.py
@@ -532,7 +532,7 @@ class LDSTCompUnit(RegSpecAPI, Elaboratable):
         # address: use sync to avoid long latency
         sync += pi.addr.data.eq(addr_r)           # EA from adder
         with m.If(op_is_dcbz):
-            sync += Display("DCBZ: EA from adder %i",addr_r)
+            sync += Display("MMUTEST.DCBZ: EA from adder %i",addr_r)
 
         sync += pi.addr.ok.eq(alu_ok & lsd_l.q)  # "do address stuff" (once)
         comb += self.exc_o.eq(pi.exc_o)  # exception occurred
diff --git a/src/soc/fu/mmu/fsm.py b/src/soc/fu/mmu/fsm.py
index c7923612..78969252 100644
--- a/src/soc/fu/mmu/fsm.py
+++ b/src/soc/fu/mmu/fsm.py
@@ -131,6 +131,7 @@ class FSMMMUStage(ControlBase):
 
             with m.Switch(op.insn_type):
                 with m.Case(MicrOp.OP_MTSPR):
+                    comb += Display("MMUTEST: OP_MTSPR: spr=%i",spr);
                     # despite redirection this FU **MUST** behave exactly
                     # like the SPR FU.  this **INCLUDES** updating the SPR
                     # regfile because the CSV file entry for OP_MTSPR
@@ -164,11 +165,13 @@ class FSMMMUStage(ControlBase):
                         comb += done.eq(1) # FIXME l_out.done
 
                 with m.Case(MicrOp.OP_MFSPR):
+                    comb += Display("MMUTEST: OP_MFSPR: spr=%i",spr);
                     comb += o.data.eq(spr1_i)
                     comb += o.ok.eq(1)
                     comb += done.eq(1)
 
                 with m.Case(MicrOp.OP_TLBIE):
+                    comb += Display("MMUTEST: OP_TLBIE: insn_bits=%i",spr);
                     # pass TLBIE request to MMU (spec: v3.0B p1034)
                     # note that the spr is *not* an actual spr number, it's
                     # just that those bits happen to match with field bits
diff --git a/src/soc/simple/test/test_issuer_mmu.py b/src/soc/simple/test/test_issuer_mmu.py
index 98fdd453..e8f14b25 100644
--- a/src/soc/simple/test/test_issuer_mmu.py
+++ b/src/soc/simple/test/test_issuer_mmu.py
@@ -18,6 +18,9 @@ import sys
 # step and comparison.
 from soc.simple.test.test_runner import TestRunner
 
+#@platen:bookmarks
+#src/openpower/test/runner.py:class TestRunnerBase(FHDLTestCase):
+
 # test with MMU
 from openpower.test.mmu.mmu_cases import MMUTestCase
 from openpower.test.mmu.mmu_rom_cases import MMUTestCaseROM, default_mem
@@ -31,9 +34,10 @@ from openpower.test.common import TestAccumulatorBase
 
 class MMUTestCase(TestAccumulatorBase):
 
+    # now working correctly
     def case_1_dcbz(self):
-        lst = ["dcbz 1, 2",
-               "dcbz 1, 3"]
+        lst = ["dcbz 1, 2",  # MMUTEST.DCBZ: EA from adder 12
+               "dcbz 1, 3"]  # MMUTEST.DCBZ: EA from adder 11
         initial_regs = [0] * 32
         initial_regs[1] = 0x0004
         initial_regs[2] = 0x0008
@@ -42,6 +46,7 @@ class MMUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                              initial_mem=initial_mem)
 
+    # MMUTEST: OP_TLBIE: insn_bits=39
     def case_2_tlbie(self):
         lst = ["tlbie 1,1,1,1,1"] # tlbie   RB,RS,RIC,PRS,R
         initial_regs = [0] * 32
@@ -49,6 +54,7 @@ class MMUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                              initial_mem=initial_mem)
 
+    # BROKEN - missing expected Display output
     def case_3_mtspr(self):
         lst = ["mtspr 720,1"] # mtspr PRTBL,r1
         initial_regs = [0] * 32
@@ -57,6 +63,7 @@ class MMUTestCase(TestAccumulatorBase):
         self.add_case(Program(lst, bigendian), initial_regs,
                              initial_mem=initial_mem)
 
+    # BROKEN - missing expected Display output
     def case_4_mfspr(self):
         lst = ["mfspr 1,18", # mtspr r1,DSISR
                "mfspr 2,19"] # mtspr r2,DAR
@@ -81,7 +88,7 @@ if __name__ == "__main__":
 
     # MMU/DCache integration tests
     suite.addTest(TestRunner(MMUTestCase().test_data, svp64=svp64,
-                              microwatt_mmu=False))
+                              microwatt_mmu=True))
 
     runner = unittest.TextTestRunner()
     runner.run(suite)