From: Nick Clifton Date: Mon, 24 Apr 2000 23:57:30 +0000 (+0000) Subject: Document behaviour of .align 0 for ARM targets. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=adcf07e61499b211183ca7135933a026764d4561;p=binutils-gdb.git Document behaviour of .align 0 for ARM targets. Remove incomplete v5e code from tc-arm.c --- diff --git a/gas/ChangeLog b/gas/ChangeLog index 6656afa02a1..3401f763d1f 100644 --- a/gas/ChangeLog +++ b/gas/ChangeLog @@ -1,3 +1,10 @@ +2000-04-24 Nick Clifton + + * doc/c-arm.texi (ARM Directives): Document behaviour of .align 0. + * doc/as.texinfo (Align): Include arm and strongarm in list of + targets that have the second form of the behaviour of the .align + directive. + 2000-04-24 Mark Klein * obj-som.c: Terminate obj_pseudo_table. diff --git a/gas/config/tc-arm.c b/gas/config/tc-arm.c index f4f73989edf..109de30b9ef 100644 --- a/gas/config/tc-arm.c +++ b/gas/config/tc-arm.c @@ -52,7 +52,6 @@ #define ARM_HALFWORD 0x00000020 /* allow half word loads */ #define ARM_THUMB 0x00000040 /* allow BX instruction */ #define ARM_EXT_V5 0x00000080 /* allow CLZ etc */ -#define ARM_EXT_V5E 0x00000200 /* "El Segundo" */ /* Architectures are the sum of the base and extensions. */ #define ARM_ARCH_V4 (ARM_7 | ARM_LONGMUL | ARM_HALFWORD) @@ -6748,7 +6747,6 @@ md_parse_option (c, arg) switch (*++str) { case 't': cpu_variant |= ARM_THUMB; break; - case 'e': cpu_variant |= ARM_EXT_V5E; break; case 0: break; default: as_bad (_("Invalid architecture variant -m%s"), arg); diff --git a/gas/doc/as.texinfo b/gas/doc/as.texinfo index f9cf578f186..ce598e581ac 100644 --- a/gas/doc/as.texinfo +++ b/gas/doc/as.texinfo @@ -3296,7 +3296,8 @@ alignment request in bytes. For example @samp{.align 8} advances the location counter until it is a multiple of 8. If the location counter is already a multiple of 8, no change is needed. -For other systems, including the i386 using a.out format, it is the +For other systems, including the i386 using a.out format, and the arm and +strongarm, it is the number of low-order zero bits the location counter must have after advancement. For example @samp{.align 3} advances the location counter until it a multiple of 8. If the location counter is already a diff --git a/gas/doc/c-arm.texi b/gas/doc/c-arm.texi index ff98d7f572c..e3549824032 100644 --- a/gas/doc/c-arm.texi +++ b/gas/doc/c-arm.texi @@ -1,4 +1,4 @@ -@c Copyright (C) 1996, 1998, 1999 Free Software Foundation, Inc. +@c Copyright (C) 1996, 1998, 1999, 2000 Free Software Foundation, Inc. @c This is part of the GAS manual. @c For copying conditions, see the file as.texinfo. @@ -27,66 +27,86 @@ @section Options @cindex ARM options (none) @cindex options for ARM (none) + @table @code + @cindex @code{-marm} command line option, ARM -@item -marm [@var{2}|@var{250}|@var{3}|@var{6}|@var{60}|@var{600}|@var{610}|@var{620}|@var{7}|@var{7m}|@var{7d}|@var{7dm}|@var{7di}|@var{7dmi}|@var{70}|@var{700}|@var{700i}|@var{710}|@var{710c}|@var{7100}|@var{7500}|@var{7500fe}|@var{7tdmi}|@var{8}|@var{810}|@var{9}|@var{9tdmi}|@var{920}|@var{strongarm}|@var{strongarm110}|@var{strongarm1100}] +@item -marm@code{[2|250|3|6|60|600|610|620|7|7m|7d|7dm|7di|7dmi|70|700|700i|710|710c|7100|7500|7500fe|7tdmi|8|810|9|9tdmi|920|strongarm|strongarm110|strongarm1100]} This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. + @cindex @code{-marmv} command line option, ARM -@item -marmv [@var{2}|@var{2a}|@var{3}|@var{3m}|@var{4}|@var{4t}|@var{5}|@var{5t}] +@item -marmv@code{[2|2a|3|3m|4|4t|5|5t]} This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. + @cindex @code{-mthumb} command line option, ARM @item -mthumb This option specifies that only Thumb instructions should be assembled. + @cindex @code{-mall} command line option, ARM @item -mall This option specifies that any Arm or Thumb instruction should be assembled. + @cindex @code{-mfpa} command line option, ARM -@item -mfpa [@var{10}|@var{11}] +@item -mfpa @var{[10|11]} This option specifies the floating point architecture in use on the target processor. + @cindex @code{-mfpe-old} command line option, ARM @item -mfpe-old Do not allow the assemble of floating point multiple instructions. + @cindex @code{-mno-fpu} command line option, ARM @item -mno-fpu Do not allow the assembly of any floating point instructions. + @cindex @code{-mthumb-interwork} command line option, ARM @item -mthumb-interwork This option specifies that the output generated by the assembler should be marked as supporting interworking. + @cindex @code{-mapcs} command line option, ARM -@item -mapcs [@var{26}|@var{32}] +@item -mapcs @var{[26|32]} This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard. + +@cindex @code{-mapcs-float} command line option, ARM @item -mapcs-float This indicates the the floating point variant of the APCS should be used. In this variant floating point arguments are passed in FP registers rather than integer registers. + +@cindex @code{-mapcs-reentrant} command line option, ARM @item -mapcs-reentrant This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code. + @cindex @code{-EB} command line option, ARM @item -EB This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor. + @cindex @code{-EL} command line option, ARM @item -EL This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor. + @cindex @code{-k} command line option, ARM @cindex PIC code generation for ARM @item -k This option enables the generation of PIC (position independent code). + +@cindex @code{-moabi} command line option, ARM @item -moabi This indicates that the code should be assembled using the old ARM ELF conventions, based on a beta release release of the ARM-ELF specifications, rather than the default conventions which are based on the final release of the ARM-ELF specifications. + @end table @@ -143,6 +163,13 @@ The ARM family uses @sc{ieee} floating-point numbers. @cindex ARM machine directives @table @code +@cindex @code{align} directive, ARM +@item .align @var{expression} [, @var{expression}] +This is the generic @var{.align} directive. For the ARM however if the +first argument is zero (ie no alignment is needed) the assembler will +behave as if the argument had been 2 (ie pad to the next four byte +boundary). This is for compatability with ARM's own assembler. + @cindex @code{req} directive, ARM @item @var{name} .req @var{register name} This creates an alias for @var{register name} called @var{name}. For @@ -153,7 +180,7 @@ example: @end smallexample @cindex @code{code} directive, ARM -@item .code [@var{16}|@var{32}] +@item .code @var{[16|32]} This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.