From: lkcl <lkcl@web>
Date: Sat, 1 Apr 2023 20:15:31 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~187
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=adfe900b70f55ff75983b5db3a8754d536cea445;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 7301f9dfb..8b5ce4377 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -483,7 +483,7 @@ it is obviously mandatory that bit 32 is required to be set to 1.
 | PO  | 0 | 1 | RM[0:23] | 1nnnnn | xxxxxxxx | SVP64:EXT232-263     |
 | PO  | 1 | 1 | RM[0:23] | nnnnnn | xxxxxxxx | SVP64:EXT000-063       |
 
-It is important to note that unlike v3.1 64-bit prefixed instructions
+It is important to note that unlike EXT1xx 64-bit prefixed instructions
 there is insufficient space in `RM` to provide identification of
 any SVP64 Fields without first partially decoding the 32-bit suffix.
 Similar to the "Forms" (X-Form, D-Form) the `RM` format is individually