From: Carl Love Date: Fri, 8 Jun 2018 15:22:31 +0000 (+0000) Subject: vsx-vector-6-be.p7.c: Rename this file to vsx-vector-6.p7.c. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=adff928a6d5fba623c579898cb92077abc970443;p=gcc.git vsx-vector-6-be.p7.c: Rename this file to vsx-vector-6.p7.c. gcc/testsuite/ChangeLog: 2018-06-08 Carl Love * gcc.target/powerpc/vsx-vector-6-be.p7.c: Rename this file to vsx-vector-6.p7.c. * gcc.target/powerpc/vsx-vector-6-le.p9.c: Rename this file to vsx-vector-6.p9.c. * gcc.target/powerpc/vsx-vector-6-be.p8.c: Move instruction counts for BE system that are different then for an LE system from this file into vsx-vector-6-le.c using be target qualifier. Remove this file. * gcc.target/powerpc/vsx-vector-6-le.c: Add le qualifiers as needed for the various instruction counts. Rename file to vsx-vector-6.p8.c. From-SVN: r261333 --- diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index d0c9e044ea2..af9b5d4e6da 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,15 @@ +2018-06-08 Carl Love + + * gcc.target/powerpc/vsx-vector-6-be.p7.c: Rename this file to + vsx-vector-6.p7.c. + * gcc.target/powerpc/vsx-vector-6-le.p9.c: Rename this file to + vsx-vector-6.p9.c. + * gcc.target/powerpc/vsx-vector-6-be.p8.c: Move instruction counts + for BE system that are different then for an LE system from this file + into vsx-vector-6-le.c using be target qualifier. Remove this file. + * gcc.target/powerpc/vsx-vector-6-le.c: Add le qualifiers as needed for + the various instruction counts. Rename file to vsx-vector-6.p8.c. + 2018-06-08 Martin Liska * gcc.dg/ipa/ipa-icf-38.c: Scan optimized tree dump. diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c deleted file mode 100644 index 835b24facef..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p7.c +++ /dev/null @@ -1,43 +0,0 @@ -/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-mvsx -O2 -mcpu=power7" } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ - - -/* Expected instruction counts for Big Endian */ - -/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ -/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ -/* { dg-final { scan-assembler-times "vperm" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ -/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ -/* { dg-final { scan-assembler-times "xxland" 13 } } */ -/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ -/* { dg-final { scan-assembler-times "xxsel" 2 } } */ -/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ -/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ - -/* Source code for the test in vsx-vector-6.h */ -#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c deleted file mode 100644 index 3b81df893d7..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-be.p8.c +++ /dev/null @@ -1,43 +0,0 @@ -/* { dg-do compile { target { powerpc64-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-mvsx -O2 -mcpu=power8" } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ - - -/* Expected instruction counts for Big Endian */ - -/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ -/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ -/* { dg-final { scan-assembler-times "vperm" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ -/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ -/* { dg-final { scan-assembler-times "xxland" 13 } } */ -/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ -/* { dg-final { scan-assembler-times "xxsel" 2 } } */ -/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ -/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ - -/* Source code for the test in vsx-vector-6.h */ -#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c deleted file mode 100644 index be5b972dced..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.c +++ /dev/null @@ -1,47 +0,0 @@ -/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_vsx_ok } */ -/* { dg-options "-mvsx -O2 -mcpu=power8" } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ - -/* Expected instruction counts for Little Endian targeting Power8. */ - -/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 8 } } */ -/* We generate xxlor instructions for many reasons other than or'ing vector - operands or calling __builtin_vec_or(), which means we cannot rely on - their usage counts being stable. Therefore, we just ensure at least one - xxlor instruction was generated. */ -/* { dg-final { scan-assembler "xxlor" } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 4 } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp." 4 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp." 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ -/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ -/* { dg-final { scan-assembler-times "vperm" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ -/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ -/* { dg-final { scan-assembler-times "xxland" 13 } } */ -/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ -/* { dg-final { scan-assembler-times "xxsel" 2 } } */ -/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ -/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ - -/* Source code for the test in vsx-vector-6.h */ -#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c deleted file mode 100644 index c2427b8cdb6..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6-le.p9.c +++ /dev/null @@ -1,37 +0,0 @@ -/* { dg-do compile { target { powerpc64le-*-* && lp64 } } } */ -/* { dg-skip-if "" { powerpc*-*-darwin* } } */ -/* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-options "-mvsx -O2 -mcpu=power9" } */ -/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ - -/* Expected instruction counts for Little Endian targeting Power9. */ - -/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ -/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ -/* We generate xxlor instructions for many reasons other than or'ing vector - operands or calling __builtin_vec_or(), which means we cannot rely on - their usage counts being stable. Therefore, we just ensure at least one - xxlor instruction was generated. */ -/* { dg-final { scan-assembler "xxlor" } } */ -/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */ -/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */ -/* { dg-final { scan-assembler-times "xvcmpgedp" 8 } } */ -/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ -/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ -/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ -/* { dg-final { scan-assembler-times "vperm" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ -/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ -/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ -/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ -/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ -/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ -/* { dg-final { scan-assembler-times "xxland" 13 } } */ - -/* Source code for the test in vsx-vector-6.h */ -#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c new file mode 100644 index 00000000000..66ec064dbff --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p7.c @@ -0,0 +1,50 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -mcpu=power7" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power7" } } */ + + +/* Expected instruction counts for Power 7 */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be }} } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp." 5 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 9 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp." 9 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 6 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 7 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp." 6 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp." 7 { target be } } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 13 } } */ +/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ +/* { dg-final { scan-assembler-times "xxsel" 2 } } */ +/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ +/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c new file mode 100644 index 00000000000..82fd45e1b63 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p8.c @@ -0,0 +1,55 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_vsx_ok } */ +/* { dg-options "-mvsx -O2 -mcpu=power8" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power8" } } */ + + +/* Expected instruction counts for Power 8. */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 8 { target le } } } */ +/* { dg-final { scan-assembler-times "xxlnor" 7 { target be } } } */ + +/* We generate xxlor instructions for many reasons other than or'ing vector + operands or calling __builtin_vec_or(), which means we cannot rely on + their usage counts being stable. Therefore, we just ensure at least one + xxlor instruction was generated. */ +/* { dg-final { scan-assembler "xxlor" } } */ + +/* { dg-final { scan-assembler-times "xvcmpeqdp" 4 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp" 6 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp." 4 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpeqdp." 6 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 7 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp." 7 { target le } } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp." 8 { target be } } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 7 } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp." 7 } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 13 } } */ +/* { dg-final { scan-assembler-times "xxlxor" 2 } } */ +/* { dg-final { scan-assembler-times "xxsel" 2 } } */ +/* { dg-final { scan-assembler-times "xvrdpip" 1 } } */ +/* { dg-final { scan-assembler-times "xvdivdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpi" 5 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h" diff --git a/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c new file mode 100644 index 00000000000..0fcd153137b --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vsx-vector-6.p9.c @@ -0,0 +1,39 @@ +/* { dg-do compile { target { powerpc*-*-* && lp64 } } } */ +/* { dg-skip-if "" { powerpc*-*-darwin* } } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mvsx -O2 -mcpu=power9" } */ +/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */ + +/* Expected instruction counts for Power9. */ + +/* { dg-final { scan-assembler-times "xvabsdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvadddp" 1 } } */ +/* { dg-final { scan-assembler-times "xxlnor" 7 } } */ + +/* We generate xxlor instructions for many reasons other than or'ing vector + operands or calling __builtin_vec_or(), which means we cannot rely on + their usage counts being stable. Therefore, we just ensure at least one + xxlor instruction was generated. */ +/* { dg-final { scan-assembler "xxlor" } } */ + +/* { dg-final { scan-assembler-times "xvcmpeqdp" 5 } } */ +/* { dg-final { scan-assembler-times "xvcmpgtdp" 8 } } */ +/* { dg-final { scan-assembler-times "xvcmpgedp" 8 } } */ +/* { dg-final { scan-assembler-times "xvrdpim" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaddadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubadp" 1 } } */ +/* { dg-final { scan-assembler-times "xvsubdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmaxdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmindp" 1 } } */ +/* { dg-final { scan-assembler-times "xvmuldp" 1 } } */ +/* { dg-final { scan-assembler-times "vperm" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpic" 1 } } */ +/* { dg-final { scan-assembler-times "xvsqrtdp" 1 } } */ +/* { dg-final { scan-assembler-times "xvrdpiz" 1 } } */ +/* { dg-final { scan-assembler-times "xvmsubasp" 1 } } */ +/* { dg-final { scan-assembler-times "xvnmaddasp" 1 } } */ +/* { dg-final { scan-assembler-times "vmsumshs" 1 } } */ +/* { dg-final { scan-assembler-times "xxland" 13 } } */ + +/* Source code for the test in vsx-vector-6.h */ +#include "vsx-vector-6.h"