From: whitequark <whitequark@whitequark.org>
Date: Sat, 11 Dec 2021 10:25:41 +0000 (+0000)
Subject: back.rtlil: extend unsigned operand of binop if another is signed.
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae095a29554ebef6012e0ec44af7731d9cafdd14;p=nmigen.git

back.rtlil: extend unsigned operand of binop if another is signed.

Fixes #580.
---

diff --git a/nmigen/back/rtlil.py b/nmigen/back/rtlil.py
index 6da4d9c..306240d 100644
--- a/nmigen/back/rtlil.py
+++ b/nmigen/back/rtlil.py
@@ -529,8 +529,8 @@ class _RHSValueCompiler(_ValueCompiler):
             lhs_wire = self(lhs)
             rhs_wire = self(rhs)
         else:
+            lhs_bits = rhs_bits = max(lhs_bits + rhs_sign, rhs_bits + lhs_sign)
             lhs_sign = rhs_sign = True
-            lhs_bits = rhs_bits = max(lhs_bits, rhs_bits)
             lhs_wire = self.match_shape(lhs, lhs_bits, lhs_sign)
             rhs_wire = self.match_shape(rhs, rhs_bits, rhs_sign)
         res_bits, res_sign = value.shape()