From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 16 Aug 2015 07:50:17 +0000 (+0200)
Subject: Fixed opt_clean handling of inout ports
X-Git-Tag: yosys-0.6~191
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae09c89f626d48bb2fa274903a220d32170b033e;p=yosys.git

Fixed opt_clean handling of inout ports
---

diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index e6de9d3c8..49615d9d6 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -90,7 +90,7 @@ void rmunused_module_cells(Module *module, bool verbose)
 	for (auto &it : module->cells_) {
 		Cell *cell = it.second;
 		for (auto &it2 : cell->connections()) {
-			if (!ct_all.cell_input(cell->type, it2.first))
+			if (!ct_all.cell_known(cell->type) || ct_all.cell_output(cell->type, it2.first))
 				for (auto bit : sigmap(it2.second))
 					if (bit.wire != nullptr)
 						wire2driver[bit].insert(cell);
@@ -115,7 +115,7 @@ void rmunused_module_cells(Module *module, bool verbose)
 		pool<SigBit> bits;
 		for (auto cell : queue)
 		for (auto &it : cell->connections())
-			if (!ct_all.cell_output(cell->type, it.first))
+			if (!ct_all.cell_known(cell->type) || ct_all.cell_input(cell->type, it.first))
 				for (auto bit : sigmap(it.second))
 					bits.insert(bit);