From: Uros Bizjak Date: Tue, 11 Sep 2018 16:42:35 +0000 (+0200) Subject: i386.md (fyl2x_extendxf3_i387): Remove. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae1ef7801810850d3192881152f7d8a3af772177;p=gcc.git i386.md (fyl2x_extendxf3_i387): Remove. * config/i386/i386.md (fyl2x_extendxf3_i387): Remove. (log2): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate logxf3 insn. (log102): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate log10xf3 insn. (log22): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate log2xf3 insn. (fyl2xp1_extendxf3_i387): Remove. (log1p2): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate log1pxf3 insn. (fxtract_extendxf3_i387): Remove. (logb2): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate logbxf3 insn. (ilogb2): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate fxtractxf3_i387 insn. (significand2): Change operand 1 predicate to general_operand. Extend operand 1 to XFmode and generate significandxf3 insn. From-SVN: r264211 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index da4995e7f5d..7a5de30e772 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,23 @@ +2018-09-11 Uros Bizjak + + * config/i386/i386.md (fyl2x_extendxf3_i387): Remove. + (log2): Change operand 1 predicate to general_operand. + Extend operand 1 to XFmode and generate logxf3 insn. + (log102): Change operand 1 predicate to general_operand. + Extend operand 1 to XFmode and generate log10xf3 insn. + (log22): Change operand 1 predicate to general_operand. + Extend operand 1 to XFmode and generate log2xf3 insn. + (fyl2xp1_extendxf3_i387): Remove. + (log1p2): Change operand 1 predicate to general_operand. + Extend operand 1 to XFmode and generate log1pxf3 insn. + (fxtract_extendxf3_i387): Remove. + (logb2): Change operand 1 predicate to general_operand. + Extend operand 1 to XFmode and generate logbxf3 insn. + (ilogb2): Change operand 1 predicate to general_operand. + Extend operand 1 to XFmode and generate fxtractxf3_i387 insn. + (significand2): Change operand 1 predicate to general_operand. + Extend operand 1 to XFmode and generate significandxf3 insn. + 2018-09-11 Nathan Sidwell * gcc.c (perror_with_name, pfatal_with_name): Delete. diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 4a0a508e2b5..44f55227592 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -15558,7 +15558,7 @@ for (i = 2; i < 6; i++) operands[i] = gen_reg_rtx (XFmode); - operands[3] = force_reg (XFmode, CONST1_RTX (XFmode)); + emit_move_insn (operands[3], CONST1_RTX (XFmode)); }) (define_expand "asin2" @@ -15596,7 +15596,7 @@ for (i = 2; i < 6; i++) operands[i] = gen_reg_rtx (XFmode); - operands[3] = force_reg (XFmode, CONST1_RTX (XFmode)); + emit_move_insn (operands[3], CONST1_RTX (XFmode)); }) (define_expand "acos2" @@ -15629,22 +15629,6 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_insn "fyl2x_extendxf3_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 1 "register_operand" "0")) - (match_operand:XF 2 "register_operand" "u")] - UNSPEC_FYL2X)) - (clobber (match_scratch:XF 3 "=2"))] - "TARGET_USE_FANCY_MATH_387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fyl2x" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) - (define_expand "logxf2" [(parallel [(set (match_operand:XF 0 "register_operand") (unspec:XF [(match_operand:XF 1 "register_operand") @@ -15653,24 +15637,23 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { - operands[2] = gen_reg_rtx (XFmode); - emit_move_insn (operands[2], standard_80387_constant_rtx (4)); /* fldln2 */ + operands[2] + = force_reg (XFmode, standard_80387_constant_rtx (4)); /* fldln2 */ }) (define_expand "log2" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); - rtx op2 = gen_reg_rtx (XFmode); - emit_move_insn (op2, standard_80387_constant_rtx (4)); /* fldln2 */ - - emit_insn (gen_fyl2x_extendxf3_i387 (op0, operands[1], op2)); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_logxf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) @@ -15683,24 +15666,23 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { - operands[2] = gen_reg_rtx (XFmode); - emit_move_insn (operands[2], standard_80387_constant_rtx (3)); /* fldlg2 */ + operands[2] + = force_reg (XFmode, standard_80387_constant_rtx (3)); /* fldlg2 */ }) (define_expand "log102" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); - rtx op2 = gen_reg_rtx (XFmode); - emit_move_insn (op2, standard_80387_constant_rtx (3)); /* fldlg2 */ - - emit_insn (gen_fyl2x_extendxf3_i387 (op0, operands[1], op2)); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_log10xf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) @@ -15712,25 +15694,21 @@ (clobber (match_scratch:XF 3))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" -{ - operands[2] = gen_reg_rtx (XFmode); - emit_move_insn (operands[2], CONST1_RTX (XFmode)); /* fld1 */ -}) + "operands[2] = force_reg (XFmode, CONST1_RTX (XFmode));") (define_expand "log22" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); - rtx op2 = gen_reg_rtx (XFmode); - emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */ - - emit_insn (gen_fyl2x_extendxf3_i387 (op0, operands[1], op2)); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_log2xf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) @@ -15748,22 +15726,6 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_insn "fyl2xp1_extendxf3_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 1 "register_operand" "0")) - (match_operand:XF 2 "register_operand" "u")] - UNSPEC_FYL2XP1)) - (clobber (match_scratch:XF 3 "=2"))] - "TARGET_USE_FANCY_MATH_387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fyl2xp1" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) - (define_expand "log1pxf2" [(use (match_operand:XF 0 "register_operand")) (use (match_operand:XF 1 "register_operand"))] @@ -15776,19 +15738,17 @@ (define_expand "log1p2" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { - rtx op0; - - op0 = gen_reg_rtx (XFmode); - - operands[1] = gen_rtx_FLOAT_EXTEND (XFmode, operands[1]); + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); - ix86_emit_i387_log1p (op0, operands[1]); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_log1pxf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; }) @@ -15806,22 +15766,6 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "XF")]) -(define_insn "fxtract_extendxf3_i387" - [(set (match_operand:XF 0 "register_operand" "=f") - (unspec:XF [(float_extend:XF - (match_operand:MODEF 2 "register_operand" "0"))] - UNSPEC_XTRACT_FRACT)) - (set (match_operand:XF 1 "register_operand" "=u") - (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_XTRACT_EXP))] - "TARGET_USE_FANCY_MATH_387 - && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - || TARGET_MIX_SSE_I387) - && flag_unsafe_math_optimizations" - "fxtract" - [(set_attr "type" "fpspc") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "XF")]) - (define_expand "logbxf2" [(parallel [(set (match_dup 2) (unspec:XF [(match_operand:XF 1 "register_operand")] @@ -15834,7 +15778,7 @@ (define_expand "logb2" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -15843,7 +15787,8 @@ rtx op0 = gen_reg_rtx (XFmode); rtx op1 = gen_reg_rtx (XFmode); - emit_insn (gen_fxtract_extendxf3_i387 (op0, op1, operands[1])); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_logbxf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op1)); DONE; }) @@ -15869,21 +15814,23 @@ (define_expand "ilogb2" [(use (match_operand:SI 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { - rtx op0, op1; + rtx op0, op1, op2; if (optimize_insn_for_size_p ()) FAIL; op0 = gen_reg_rtx (XFmode); op1 = gen_reg_rtx (XFmode); + op2 = gen_reg_rtx (XFmode); - emit_insn (gen_fxtract_extendxf3_i387 (op0, op1, operands[1])); + emit_insn (gen_extendxf2 (op2, operands[1])); + emit_insn (gen_fxtractxf3_i387 (op0, op1, op2)); emit_insn (gen_fix_truncxfsi2 (operands[0], op1)); DONE; }) @@ -15935,7 +15882,7 @@ for (i = 3; i < 10; i++) operands[i] = gen_reg_rtx (XFmode); - emit_move_insn (operands[7], CONST1_RTX (XFmode)); /* fld1 */ + emit_move_insn (operands[7], CONST1_RTX (XFmode)); }) (define_expand "expxf2" @@ -15944,10 +15891,7 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { - rtx op2; - - op2 = gen_reg_rtx (XFmode); - emit_move_insn (op2, standard_80387_constant_rtx (5)); /* fldl2e */ + rtx op2 = force_reg (XFmode, standard_80387_constant_rtx (5)); /* fldl2e */ emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2)); DONE; @@ -15961,10 +15905,8 @@ || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { - rtx op0, op1; - - op0 = gen_reg_rtx (XFmode); - op1 = gen_reg_rtx (XFmode); + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_expxf2 (op0, op1)); @@ -15978,10 +15920,7 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { - rtx op2; - - op2 = gen_reg_rtx (XFmode); - emit_move_insn (op2, standard_80387_constant_rtx (6)); /* fldl2t */ + rtx op2 = force_reg (XFmode, standard_80387_constant_rtx (6)); /* fldl2t */ emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2)); DONE; @@ -15995,10 +15934,8 @@ || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { - rtx op0, op1; - - op0 = gen_reg_rtx (XFmode); - op1 = gen_reg_rtx (XFmode); + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_exp10xf2 (op0, op1)); @@ -16012,10 +15949,7 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { - rtx op2; - - op2 = gen_reg_rtx (XFmode); - emit_move_insn (op2, CONST1_RTX (XFmode)); /* fld1 */ + rtx op2 = force_reg (XFmode, CONST1_RTX (XFmode)); emit_insn (gen_expNcorexf3 (operands[0], operands[1], op2)); DONE; @@ -16029,10 +15963,8 @@ || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { - rtx op0, op1; - - op0 = gen_reg_rtx (XFmode); - op1 = gen_reg_rtx (XFmode); + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_exp2xf2 (op0, op1)); @@ -16045,7 +15977,6 @@ (match_dup 2))) (set (match_dup 4) (unspec:XF [(match_dup 3)] UNSPEC_FRNDINT)) (set (match_dup 5) (minus:XF (match_dup 3) (match_dup 4))) - (set (match_dup 9) (float_extend:XF (match_dup 13))) (set (match_dup 6) (unspec:XF [(match_dup 5)] UNSPEC_F2XM1)) (parallel [(set (match_dup 7) (unspec:XF [(match_dup 6) (match_dup 4)] @@ -16059,8 +15990,7 @@ (set (match_dup 11) (unspec:XF [(match_dup 9) (match_dup 8)] UNSPEC_FSCALE_EXP))]) - (set (match_dup 12) (minus:XF (match_dup 10) - (float_extend:XF (match_dup 13)))) + (set (match_dup 12) (minus:XF (match_dup 10) (match_dup 9))) (set (match_operand:XF 0 "register_operand") (plus:XF (match_dup 12) (match_dup 7)))] "TARGET_USE_FANCY_MATH_387 @@ -16071,10 +16001,8 @@ for (i = 2; i < 13; i++) operands[i] = gen_reg_rtx (XFmode); - operands[13] - = validize_mem (force_const_mem (SFmode, CONST1_RTX (SFmode))); /* fld1 */ - emit_move_insn (operands[2], standard_80387_constant_rtx (5)); /* fldl2e */ + emit_move_insn (operands[9], CONST1_RTX (XFmode)); }) (define_expand "expm12" @@ -16085,10 +16013,8 @@ || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { - rtx op0, op1; - - op0 = gen_reg_rtx (XFmode); - op1 = gen_reg_rtx (XFmode); + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_expm1xf2 (op0, op1)); @@ -16103,10 +16029,8 @@ "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" { - rtx tmp1, tmp2; - - tmp1 = gen_reg_rtx (XFmode); - tmp2 = gen_reg_rtx (XFmode); + rtx tmp1 = gen_reg_rtx (XFmode); + rtx tmp2 = gen_reg_rtx (XFmode); emit_insn (gen_floatsixf2 (tmp1, operands[2])); emit_insn (gen_fscalexf4_i387 (operands[0], tmp2, @@ -16123,10 +16047,8 @@ || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { - rtx op0, op1; - - op0 = gen_reg_rtx (XFmode); - op1 = gen_reg_rtx (XFmode); + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_ldexpxf3 (op0, op1, operands[2])); @@ -16144,9 +16066,7 @@ UNSPEC_FSCALE_EXP))])] "TARGET_USE_FANCY_MATH_387 && flag_unsafe_math_optimizations" -{ - operands[3] = gen_reg_rtx (XFmode); -}) + "operands[3] = gen_reg_rtx (XFmode);") (define_expand "scalb3" [(use (match_operand:MODEF 0 "register_operand")) @@ -16157,11 +16077,9 @@ || TARGET_MIX_SSE_I387) && flag_unsafe_math_optimizations" { - rtx op0, op1, op2; - - op0 = gen_reg_rtx (XFmode); - op1 = gen_reg_rtx (XFmode); - op2 = gen_reg_rtx (XFmode); + rtx op0 = gen_reg_rtx (XFmode); + rtx op1 = gen_reg_rtx (XFmode); + rtx op2 = gen_reg_rtx (XFmode); emit_insn (gen_extendxf2 (op1, operands[1])); emit_insn (gen_extendxf2 (op2, operands[2])); @@ -16182,7 +16100,7 @@ (define_expand "significand2" [(use (match_operand:MODEF 0 "register_operand")) - (use (match_operand:MODEF 1 "register_operand"))] + (use (match_operand:MODEF 1 "general_operand"))] "TARGET_USE_FANCY_MATH_387 && (!(SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387) @@ -16191,7 +16109,8 @@ rtx op0 = gen_reg_rtx (XFmode); rtx op1 = gen_reg_rtx (XFmode); - emit_insn (gen_fxtract_extendxf3_i387 (op0, op1, operands[1])); + emit_insn (gen_extendxf2 (op1, operands[1])); + emit_insn (gen_significandxf2 (op0, op1)); emit_insn (gen_truncxf2 (operands[0], op0)); DONE; })