From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 12 Sep 2020 22:21:22 +0000 (+0100)
Subject: missing reservation address comparison
X-Git-Tag: semi_working_ecp5~84
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae266b309180b9b820cc8d4e34133c4e60ae17b2;p=soc.git

missing reservation address comparison
---

diff --git a/src/soc/experiment/dcache.py b/src/soc/experiment/dcache.py
index abf6c276..5e797f41 100644
--- a/src/soc/experiment/dcache.py
+++ b/src/soc/experiment/dcache.py
@@ -935,14 +935,14 @@ class DCache(Elaboratable):
         sync = m.d.sync
 
         with m.If(r0_valid & r0.req.reserve):
-
             # XXX generate alignment interrupt if address
             # is not aligned XXX or if r0.req.nc = '1'
             with m.If(r0.req.load):
                 comb += set_rsrv.eq(1) # load with reservation
             with m.Else():
                 comb += clear_rsrv.eq(1) # store conditional
-                with m.If(~reservation.valid | r0.req.addr[LINE_OFF_BITS:64]):
+                with m.If(~reservation.valid |
+                         (r0.req.addr[LINE_OFF_BITS:64] != reservation.addr)):
                     comb += cancel_store.eq(1)
 
     def reservation_reg(self, m, r0_valid, access_ok, set_rsrv, clear_rsrv,