From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Wed, 31 Jul 2019 23:18:39 +0000 (+0100)
Subject: comment
X-Git-Tag: ls180-24jan2020~585
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae35735d0b5c6c3c5c2778af6d37d3c96c0a01e3;p=ieee754fpu.git

comment
---

diff --git a/src/ieee754/fcvt/downsize.py b/src/ieee754/fcvt/downsize.py
index b76e3f5e..c02dedee 100644
--- a/src/ieee754/fcvt/downsize.py
+++ b/src/ieee754/fcvt/downsize.py
@@ -72,7 +72,7 @@ class FPCVTDownConvertMod(PipeModBase):
             comb += self.o.of.guard.eq(a1.m[ms-1])
             comb += self.o.of.round_bit.eq(a1.m[ms-2])
             comb += self.o.of.sticky.eq(a1.m[:ms-2].bool())
-            comb += self.o.of.m0.eq(a1.m[ms])  # bit of a1
+            comb += self.o.of.m0.eq(a1.m[ms])  # LSB bit of a1
 
             comb += self.o.z.s.eq(a1.s)
             comb += self.o.z.e.eq(a1.e)