From: Andrew Waterman <waterman@s141.Millennium.Berkeley.EDU>
Date: Thu, 5 Aug 2010 03:28:47 +0000 (-0700)
Subject: [sim] Bug fixes in shifts, plus a new test case
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae3bcd0a39ddd8538cd136dbae6ef14344405114;p=riscv-isa-sim.git

[sim] Bug fixes in shifts, plus a new test case
---

diff --git a/riscv/insns/srav.h b/riscv/insns/srav.h
index ec6fee8..e01fcd5 100644
--- a/riscv/insns/srav.h
+++ b/riscv/insns/srav.h
@@ -1,2 +1,2 @@
 require64;
-RC = RB >> (RA & 0x3F);
+RC = sreg_t(RB) >> (RA & 0x3F);
diff --git a/riscv/insns/srlvw.h b/riscv/insns/srlvw.h
index 7e1755f..c523b59 100644
--- a/riscv/insns/srlvw.h
+++ b/riscv/insns/srlvw.h
@@ -1 +1 @@
-RC = sext32(RB >> (RA & 0x1F));
+RC = sext32((uint32_t)RB >> (RA & 0x1F));
diff --git a/riscv/insns/srlw.h b/riscv/insns/srlw.h
index 0537a1c..9e41c8c 100644
--- a/riscv/insns/srlw.h
+++ b/riscv/insns/srlw.h
@@ -1 +1 @@
-RC = sext32(RB >> SHAMT);
+RC = sext32((uint32_t)RB >> SHAMT);