From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 22 Sep 2020 11:47:49 +0000 (+0100)
Subject: add JTAG IOpads and rename rst to sys_rst
X-Git-Tag: 24jan2021_ls180~355
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae414655df64a1ca4eb3f697981ddb8e77bd5b00;p=soc.git

add JTAG IOpads and rename rst to sys_rst
---

diff --git a/src/soc/litex/florent/libresoc/ls180.py b/src/soc/litex/florent/libresoc/ls180.py
index 01823135..bcf363b5 100644
--- a/src/soc/litex/florent/libresoc/ls180.py
+++ b/src/soc/litex/florent/libresoc/ls180.py
@@ -23,7 +23,14 @@ import os
 
 _io = [
     ("sys_clk", 0, Pins("G2"), IOStandard("LVCMOS33")),
-    ("rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
+    ("sys_rst",   0, Pins("R1"), IOStandard("LVCMOS33")),
+
+    ("jtag", 0,
+        Subsignal("tms", Pins("Z1"), IOStandard("LVCMOS33")),
+        Subsignal("tck", Pins("Z2"), IOStandard("LVCMOS33")),
+        Subsignal("tdi", Pins("Z3"), IOStandard("LVCMOS33")),
+        Subsignal("tdo", Pins("Z4"), IOStandard("LVCMOS33")),
+    ),
 
     ("serial", 0,
         Subsignal("tx", Pins("L4"), IOStandard("LVCMOS33")),