From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 15 Aug 2021 22:07:28 +0000 (+0100)
Subject: add subTest back in to bcd tst
X-Git-Tag: xlen-bcd~122
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae564ae27e08a980af7bdb574c4be81bf6eb3bf6;p=openpower-isa.git

add subTest back in to bcd tst
---

diff --git a/src/openpower/decoder/isa/test_caller_bcd.py b/src/openpower/decoder/isa/test_caller_bcd.py
index 006b7214..f69a5098 100644
--- a/src/openpower/decoder/isa/test_caller_bcd.py
+++ b/src/openpower/decoder/isa/test_caller_bcd.py
@@ -281,12 +281,13 @@ class BCDTestCase(FHDLTestCase):
     def run_tst(self, instr, mapping):
         lst = [f"{instr} {reg}, {reg}" for reg in range(32)]
         for (iregs, oregs) in testgen(mapping):
-            with Program(lst, bigendian=False) as program:
-                sim = self.run_tst_program(program, iregs)
-                gprs = [sim.gpr(gpr) for gpr in range(32)]
-                for gpr in range(32):
-                    self.assertEqual(sim.gpr(gpr),
-                                     SelectableInt(oregs[gpr], 64))
+            with self.subTest():
+                with Program(lst, bigendian=False) as program:
+                    sim = self.run_tst_program(program, iregs)
+                    gprs = [sim.gpr(gpr) for gpr in range(32)]
+                    for gpr in range(32):
+                        self.assertEqual(sim.gpr(gpr),
+                                         SelectableInt(oregs[gpr], 64))
 
     @unittest.skip("")
     def test_cdtbcd(self):