From: Jacob Lifshay Date: Thu, 25 Aug 2022 04:14:21 +0000 (-0700) Subject: change test cases to use TestRunnerBase in order to not need soc X-Git-Tag: sv_maxu_works-initial~114 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae64e1eee4fecb9ad8e8655a232047cd595ab5b4;p=openpower-isa.git change test cases to use TestRunnerBase in order to not need soc --- diff --git a/src/openpower/decoder/isa/test_caller_alu.py b/src/openpower/decoder/isa/test_caller_alu.py index 155d1a98..9011ef62 100644 --- a/src/openpower/decoder/isa/test_caller_alu.py +++ b/src/openpower/decoder/isa/test_caller_alu.py @@ -10,7 +10,7 @@ import sys # These tests utilize the run_hdl=False parameter to compare # simulator with expected states -from soc.simple.test.test_runner import TestRunner +from openpower.test.runner import TestRunnerBase from openpower.test.alu.alu_cases import ALUTestCase @@ -32,7 +32,7 @@ if __name__ == "__main__": # walk through all tests, those requested get added for tname, data in tests.items(): if tname in testing: - suite.addTest(TestRunner(data, run_hdl=False)) + suite.addTest(TestRunnerBase(data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/openpower/decoder/isa/test_caller_bitmanip.py b/src/openpower/decoder/isa/test_caller_bitmanip.py index 4c5db091..6ba5f661 100644 --- a/src/openpower/decoder/isa/test_caller_bitmanip.py +++ b/src/openpower/decoder/isa/test_caller_bitmanip.py @@ -10,7 +10,7 @@ import sys # These tests utilize the run_hdl=False parameter to compare # simulator with expected states -from soc.simple.test.test_runner import TestRunner +from openpower.test.runner import TestRunnerBase from openpower.test.bitmanip.bitmanip_cases import BitManipTestCase @@ -32,7 +32,7 @@ if __name__ == "__main__": # walk through all tests, those requested get added for tname, data in tests.items(): if tname in testing: - suite.addTest(TestRunner(data, run_hdl=False)) + suite.addTest(TestRunnerBase(data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/openpower/decoder/isa/test_caller_bitmanip_av.py b/src/openpower/decoder/isa/test_caller_bitmanip_av.py index 9c4788fc..4e5cf97a 100644 --- a/src/openpower/decoder/isa/test_caller_bitmanip_av.py +++ b/src/openpower/decoder/isa/test_caller_bitmanip_av.py @@ -10,7 +10,7 @@ import sys # These tests utilize the run_hdl=False parameter to compare # simulator with expected states -from soc.simple.test.test_runner import TestRunner +from openpower.test.runner import TestRunnerBase from openpower.test.bitmanip.av_cases import AVTestCase @@ -32,7 +32,7 @@ if __name__ == "__main__": # walk through all tests, those requested get added for tname, data in tests.items(): if tname in testing: - suite.addTest(TestRunner(data, run_hdl=False)) + suite.addTest(TestRunnerBase(data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/openpower/decoder/isa/test_caller_fmvis.py b/src/openpower/decoder/isa/test_caller_fmvis.py index 63e923d6..1c7638a4 100644 --- a/src/openpower/decoder/isa/test_caller_fmvis.py +++ b/src/openpower/decoder/isa/test_caller_fmvis.py @@ -10,7 +10,7 @@ import sys # These tests utilize the run_hdl=False parameter to compare # simulator with expected states -from soc.simple.test.test_runner import TestRunner +from openpower.test.runner import TestRunnerBase from openpower.test.alu.fmvis_cases import FMVISTestCase @@ -32,7 +32,7 @@ if __name__ == "__main__": # walk through all tests, those requested get added for tname, data in tests.items(): if tname in testing: - suite.addTest(TestRunner(data, run_hdl=False)) + suite.addTest(TestRunnerBase(data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/openpower/decoder/isa/test_caller_logical.py b/src/openpower/decoder/isa/test_caller_logical.py index eb3282b4..9546319f 100644 --- a/src/openpower/decoder/isa/test_caller_logical.py +++ b/src/openpower/decoder/isa/test_caller_logical.py @@ -10,7 +10,7 @@ import sys # These tests utilize the run_hdl=False parameter to compare # simulator with expected states -from soc.simple.test.test_runner import TestRunner +from openpower.test.runner import TestRunnerBase from openpower.test.logical.logical_cases import LogicalTestCase @@ -32,7 +32,7 @@ if __name__ == "__main__": # walk through all tests, those requested get added for tname, data in tests.items(): if tname in testing: - suite.addTest(TestRunner(data, run_hdl=False)) + suite.addTest(TestRunnerBase(data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/openpower/decoder/isa/test_caller_mul.py b/src/openpower/decoder/isa/test_caller_mul.py index cb2e218d..824d3a93 100644 --- a/src/openpower/decoder/isa/test_caller_mul.py +++ b/src/openpower/decoder/isa/test_caller_mul.py @@ -10,7 +10,7 @@ import sys # These tests utilize the run_hdl=False parameter to compare # simulator with expected states -from soc.simple.test.test_runner import TestRunner +from openpower.test.runner import TestRunnerBase from openpower.test.mul.mul_cases import MulTestCases2Arg @@ -32,7 +32,7 @@ if __name__ == "__main__": # walk through all tests, those requested get added for tname, data in tests.items(): if tname in testing: - suite.addTest(TestRunner(data, run_hdl=False)) + suite.addTest(TestRunnerBase(data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/openpower/decoder/isa/test_caller_shift_rot.py b/src/openpower/decoder/isa/test_caller_shift_rot.py index 04a0e4a9..6d0a949f 100644 --- a/src/openpower/decoder/isa/test_caller_shift_rot.py +++ b/src/openpower/decoder/isa/test_caller_shift_rot.py @@ -10,7 +10,7 @@ import sys # These tests utilize the run_hdl=False parameter to compare # simulator with expected states -from soc.simple.test.test_runner import TestRunner +from openpower.test.runner import TestRunnerBase from openpower.test.shift_rot.shift_rot_cases2 import ShiftRotTestCase2 @@ -32,7 +32,7 @@ if __name__ == "__main__": # walk through all tests, those requested get added for tname, data in tests.items(): if tname in testing: - suite.addTest(TestRunner(data, run_hdl=False)) + suite.addTest(TestRunnerBase(data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/openpower/decoder/isa/test_caller_svp64_alu.py b/src/openpower/decoder/isa/test_caller_svp64_alu.py index c46d31a0..1a294d5d 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_alu.py +++ b/src/openpower/decoder/isa/test_caller_svp64_alu.py @@ -10,7 +10,7 @@ import sys # These tests utilize the run_hdl=False parameter to compare # simulator with expected states -from soc.simple.test.test_runner import TestRunner +from openpower.test.runner import TestRunnerBase from openpower.test.alu.svp64_cases import SVP64ALUTestCase @@ -32,7 +32,7 @@ if __name__ == "__main__": # walk through all tests, those requested get added for tname, data in tests.items(): if tname in testing: - suite.addTest(TestRunner(data, run_hdl=False)) + suite.addTest(TestRunnerBase(data)) runner = unittest.TextTestRunner() runner.run(suite) diff --git a/src/openpower/decoder/isa/test_caller_svp64_logical.py b/src/openpower/decoder/isa/test_caller_svp64_logical.py index 483b2477..bc600cf7 100644 --- a/src/openpower/decoder/isa/test_caller_svp64_logical.py +++ b/src/openpower/decoder/isa/test_caller_svp64_logical.py @@ -10,7 +10,7 @@ import sys # These tests utilize the run_hdl=False parameter to compare # simulator with expected states -from soc.simple.test.test_runner import TestRunner +from openpower.test.runner import TestRunnerBase from openpower.test.logical.svp64_cases import SVP64LogicalTestCase @@ -32,7 +32,7 @@ if __name__ == "__main__": # walk through all tests, those requested get added for tname, data in tests.items(): if tname in testing: - suite.addTest(TestRunner(data, run_hdl=False)) + suite.addTest(TestRunnerBase(data)) runner = unittest.TextTestRunner() runner.run(suite)