From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Mon, 29 Aug 2022 20:37:34 +0000 (+0100)
Subject: add a "ffmadds." test, not yet actually checking Rc=1
X-Git-Tag: sv_maxu_works-initial~14
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae711cbf741efb8a0e2845054477c698567c2b48;p=openpower-isa.git

add a "ffmadds." test, not yet actually checking Rc=1
---

diff --git a/src/openpower/decoder/isa/caller.py b/src/openpower/decoder/isa/caller.py
index 39e195ca..cf85d428 100644
--- a/src/openpower/decoder/isa/caller.py
+++ b/src/openpower/decoder/isa/caller.py
@@ -445,6 +445,9 @@ def get_pdecode_cr_out(dec2, name):
     if name == 'CR0':
         if out_sel == CROutSel.CR0.value:
             return out, o_isvec
+    if name == 'CR1': # these are not actually calculated correctly
+        if out_sel == CROutSel.CR1.value:
+            return out, o_isvec
     log("get_pdecode_cr_out not found", name)
     return None, False
 
@@ -1381,7 +1384,11 @@ class ISACaller(ISACallerHelper, ISAFPHelpers):
             if hasattr(self.dec2.e.do, "rc"):
                 rc_en = yield self.dec2.e.do.rc.rc
         if rc_en and ins_name not in ['svstep']:
-            regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, "CR0")
+            if ins_name.startswith("f"):
+                rc_reg = "CR1" # not calculated correctly yet (not FP compares)
+            else:
+                rc_reg = "CR0"
+            regnum, is_vec = yield from get_pdecode_cr_out(self.dec2, rc_reg)
             cmps = results
             # hang on... for `setvl` actually you want to test SVSTATE.VL
             is_setvl = ins_name == 'setvl'
diff --git a/src/openpower/decoder/isa/test_caller_svp64_fft.py b/src/openpower/decoder/isa/test_caller_svp64_fft.py
index 114e8853..cf5915ad 100644
--- a/src/openpower/decoder/isa/test_caller_svp64_fft.py
+++ b/src/openpower/decoder/isa/test_caller_svp64_fft.py
@@ -137,6 +137,59 @@ class FFTTestCase(FHDLTestCase):
         for i in range(32):
             self.assertEqual(sim.gpr(i), SelectableInt(expected[i], 64))
 
+    def test_sv_remap_fpmadds_fft_4(self):
+        """>>> lst = ["svshape 2, 1, 1, 1, 0",
+                     "svremap 31, 1, 0, 2, 0, 1, 0",
+                      "sv.ffmadds. *2, *2, *2, *10"
+                     ]
+        this is a cheap (cheating) way to run a single "ffmadds." to
+        get at least Rc=1 on sv.ffmadds to be activated. the results
+        are not actually tested because there's no checking yet on
+        FP Rc=1
+        """
+        lst = SVP64Asm( ["svshape 2, 1, 1, 1, 0",
+                         "svremap 31, 1, 0, 2, 0, 1, 0",
+                        "sv.ffmadds *0, *0, *0, *8"
+                        ])
+        lst = list(lst)
+
+        # array and coefficients to test
+        av = [7.0, -9.8 ] # array 0..1
+        coe = [3.1] # coefficients
+
+        # store in regfile
+        fprs = [0] * 32
+        for i, c in enumerate(coe):
+            fprs[i+8] = fp64toselectable(c)
+        for i, a in enumerate(av):
+            fprs[i+0] = fp64toselectable(a)
+
+        with Program(lst, bigendian=False) as program:
+            sim = self.run_tst_program(program, initial_fprs=fprs)
+            print ("spr svshape0", sim.spr['SVSHAPE0'])
+            print ("    xdimsz", sim.spr['SVSHAPE0'].xdimsz)
+            print ("    ydimsz", sim.spr['SVSHAPE0'].ydimsz)
+            print ("    zdimsz", sim.spr['SVSHAPE0'].zdimsz)
+            print ("spr svshape1", sim.spr['SVSHAPE1'])
+            print ("spr svshape2", sim.spr['SVSHAPE2'])
+            print ("spr svshape3", sim.spr['SVSHAPE3'])
+
+            # work out the results with the twin mul/add-sub
+            res = transform_radix2(av, coe)
+
+            for i, expected in enumerate(res):
+                print ("i", i, float(sim.fpr(i)), "expected", expected)
+            for i, expected in enumerate(res):
+                # convert to Power single
+                expected = fph.DOUBLE2SINGLE(fp64toselectable(expected))
+                expected = float(expected)
+                actual = float(sim.fpr(i))
+                # approximate error calculation, good enough test
+                # reason: we are comparing FMAC against FMUL-plus-FADD-or-FSUB
+                # and the rounding is different
+                err = abs(actual - expected) / expected
+                self.assertTrue(err < 1e-7)
+
     def test_sv_remap_fpmadds_fft(self):
         """>>> lst = ["svshape 8, 1, 1, 1, 0",
                      "svremap 31, 1, 0, 2, 0, 1, 0",