From: Jacob Lifshay Date: Wed, 17 Nov 2021 19:25:21 +0000 (-0800) Subject: rename ternary->ternlog and associated form/field TI->TLI X-Git-Tag: sv_maxu_works-initial~730 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae770cc6c2d648a020c8a0ed0447211933c25d3e;p=openpower-isa.git rename ternary->ternlog and associated form/field TI->TLI --- diff --git a/openpower/isatables/RM-1P-3S1D.csv b/openpower/isatables/RM-1P-3S1D.csv index cdb0207e..c25ac728 100644 --- a/openpower/isatables/RM-1P-3S1D.csv +++ b/openpower/isatables/RM-1P-3S1D.csv @@ -31,7 +31,7 @@ isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 isel,,1P,EXTRA2,d:RT,s:RA,s:RB,s:BC,RA_OR_ZERO,RB,0,RT,BC,0,0 -ternaryi,,1P,EXTRA2,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 +ternlogi,,1P,EXTRA2,d:RT;d:CR0,s:RA,s:RB,s:RT,RA,RB,RT,RT,0,CR0,0 ffmsubs,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 ffmadds,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 ffnmsubs,,1P,EXTRA2,d:FRT;d:CR1,s:FRA,s:FRB,s:FRC,FRA,FRB,FRC,FRT,0,CR1,0 diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index 871cd743..bf9b055c 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -283,9 +283,9 @@ |0 |6 |11 |13 |15 |17 |19 |21 |22 |26 |31 | | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 |pst |/// | XO | / | -# 1.6.34 TI-FORM - |0 |6 |11 |16 |21 |29 |31 | - | PO | RT | RA | RB | TI | XO |Rc | +# 1.6.34 TLI-FORM + |0 |6 |11 |16 |21 |29 |31 | + | PO | RT | RA | RB | TLI | XO |Rc | # 1.6.28 Instruction Fields A (6) @@ -828,10 +828,10 @@ and dcbtst instructions (see Section 4.3.2 of Book II). Formats: X - TI (21:28) - Field used by the ternaryi instruction as the + TLI (21:28) + Field used by the ternlogi instruction as the look-up table. - Formats: TI + Formats: TLI TO (6:10) Field used to specify the conditions on which to trap. The encoding is described in @@ -958,7 +958,7 @@ Formats: MDS XO (29:30) Extended opcode field. - Formats: TI + Formats: TLI XO (29:31) Extended opcode field. Formats: DQ diff --git a/openpower/isatables/minor_5.csv b/openpower/isatables/minor_5.csv index 617c2e17..37ccbc8b 100644 --- a/openpower/isatables/minor_5.csv +++ b/openpower/isatables/minor_5.csv @@ -1,2 +1,2 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS,unofficial,comment2 ---------00-,ALU,OP_TERNARY,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternaryi,TI,,1,unofficial until submitted and approved/renumbered by the opf isa wg +--------00-,ALU,OP_TERNLOG,RA,RB,RT,RT,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,ternlogi,TLI,,1,unofficial until submitted and approved/renumbered by the opf isa wg diff --git a/src/openpower/decoder/power_decoder2.py b/src/openpower/decoder/power_decoder2.py index 2fa6feac..49ab5066 100644 --- a/src/openpower/decoder/power_decoder2.py +++ b/src/openpower/decoder/power_decoder2.py @@ -365,7 +365,7 @@ class DecodeC(Elaboratable): comb += reg.data.eq(self.dec.RC) comb += reg.ok.eq(1) with m.Case(In3Sel.RT): - # for TI-form ternary + # for TLI-form ternlogi comb += reg.data.eq(self.dec.RT) comb += reg.ok.eq(1) diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index 477e472a..86a9c288 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -120,7 +120,7 @@ class Form(Enum): SVDS = 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form SVM = 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY SVRM = 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY - TI = 34 # ternaryi + TLI = 34 # ternlogi # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/ @@ -330,7 +330,7 @@ _insns = [ "subf", "subfc", "subfco", "subfe", "subfeo", "subfic", "subfme", "subfmeo", "subfo", "subfze", "subfzeo", "sync", - "ternaryi", + "ternlogi", "td", "tdi", "tlbie", "tlbiel", "tw", "twi", @@ -435,7 +435,7 @@ class MicrOp(Enum): OP_ADDG6S = 83 OP_CDTBCD = 84 OP_CBCDTD = 85 - OP_TERNARY = 86 + OP_TERNLOG = 86 @unique @@ -478,7 +478,7 @@ class In3Sel(Enum): FRS = 3 FRC = 4 RC = 5 # for SVP64 bit-reverse LD/ST - RT = 6 # for ternary[i] + RT = 6 # for ternlog[i] @unique