From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 26 Jun 2020 17:58:38 +0000 (+0100)
Subject: whitespace
X-Git-Tag: div_pipeline~259
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae7924c0df38f0b1f6030105e26c50be793a8a95;p=soc.git

whitespace
---

diff --git a/src/soc/experiment/lsmem.py b/src/soc/experiment/lsmem.py
index e9260176..d8292920 100644
--- a/src/soc/experiment/lsmem.py
+++ b/src/soc/experiment/lsmem.py
@@ -20,8 +20,8 @@ class TestMemLoadStoreUnit(LoadStoreUnitInterface, Elaboratable):
         # limit TestMemory to 2^6 entries of regwid size
         m.submodules.mem = mem = TestMemory(regwid, 6, granularity=8)
 
-        do_load = Signal()  # set when doing a load while valid and not stalled
-        do_store = Signal() # set when doing a store while valid and not stalled
+        do_load = Signal()  # set when load while valid and not stalled
+        do_store = Signal() # set when store while valid and not stalled
 
         m.d.comb += [
             do_load.eq(self.x_ld_i & (self.x_valid_i & ~self.x_stall_i)),