From: Clifford Wolf <clifford@clifford.at>
Date: Sun, 24 Nov 2013 16:55:46 +0000 (+0100)
Subject: Fixed xilinx/example_sim_counter test bench
X-Git-Tag: yosys-0.2.0~312
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae798d3fd5dc6bdd82083cce3994f449b829995e;p=yosys.git

Fixed xilinx/example_sim_counter test bench
---

diff --git a/techlibs/xilinx/example_sim_counter/run_sim.sh b/techlibs/xilinx/example_sim_counter/run_sim.sh
index e26d00db1..b8354c002 100644
--- a/techlibs/xilinx/example_sim_counter/run_sim.sh
+++ b/techlibs/xilinx/example_sim_counter/run_sim.sh
@@ -8,7 +8,7 @@ XILINX_DIR=/opt/Xilinx/14.5/ISE_DS/ISE
 
 iverilog -o testbench_gold counter_tb.v counter.v
 iverilog -o testbench_gate counter_tb.v testbench_synth.v \
-	$XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6}}.v
+	$XILINX_DIR/verilog/src/{glbl,unisims/{FDRE,LUT1,LUT2,LUT3,LUT4,LUT5,LUT6,BUFGP,IBUF}}.v
 
 ./testbench_gold > testbench_gold.txt
 ./testbench_gate > testbench_gate.txt