From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 23 May 2019 15:58:57 +0000 (-0700)
Subject: Add whitebox support to DRAM
X-Git-Tag: working-ls180~1208^2~285
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae89e6ab26d2d87a604e20ebc14dcda8c9901585;p=yosys.git

Add whitebox support to DRAM
---

diff --git a/techlibs/xilinx/abc.box b/techlibs/xilinx/abc.box
index 57ea1670c..92ea5537b 100644
--- a/techlibs/xilinx/abc.box
+++ b/techlibs/xilinx/abc.box
@@ -25,3 +25,17 @@ CARRY4 3 1 10 8
 -   469 548 528 -   205 558 618
 -   -   292 376 -   -   226 330
 -   -   -   380 -   -   -   227
+
+# SLICEM/A6LUT
+# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
+# Outputs: DPO SPO
+RAM64X1D 4 1 15 2
+-   -   -   -   -   -   - 124 124 124 124 124 124 - -
+124 124 124 124 124 124 - -   -   -   -   -   124 - -
+
+# SLICEM/A6LUT + F7[AB]MUX
+# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
+# Outputs: DPO SPO
+RAM128X1D 5 1 17 2
+-   -   -   -   -   -   -   - 314 314 314 314 314 314 292 - -
+347 347 347 347 347 347 296 - -   -   -   -   -   -   -   - -
diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v
index 9db52b67a..29c79f689 100644
--- a/techlibs/xilinx/cells_sim.v
+++ b/techlibs/xilinx/cells_sim.v
@@ -281,8 +281,9 @@ module FDPE_1 ((* abc_flop_q *) output reg Q, input C, CE, D, PRE);
   always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
 endmodule
 
+(* abc_box_id = 4, lib_whitebox *)
 module RAM64X1D (
-  (* abc_flop_q *) output DPO, SPO,
+  output DPO, SPO,
   input  D, WCLK, WE,
   input  A0, A1, A2, A3, A4, A5,
   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5
@@ -294,12 +295,15 @@ module RAM64X1D (
   reg [63:0] mem = INIT;
   assign SPO = mem[a];
   assign DPO = mem[dpra];
+`ifndef _ABC
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[a] <= D;
+`endif
 endmodule
 
+(* abc_box_id = 5, lib_whitebox *)
 module RAM128X1D (
-  (* abc_flop_q *) output       DPO, SPO,
+  output       DPO, SPO,
   input        D, WCLK, WE,
   input  [6:0] A, DPRA
 );
@@ -308,8 +312,10 @@ module RAM128X1D (
   reg [127:0] mem = INIT;
   assign SPO = mem[A];
   assign DPO = mem[DPRA];
+`ifndef _ABC
   wire clk = WCLK ^ IS_WCLK_INVERTED;
   always @(posedge clk) if (WE) mem[A] <= D;
+`endif
 endmodule
 
 module SRL16E (
diff --git a/techlibs/xilinx/cells_xtra.sh b/techlibs/xilinx/cells_xtra.sh
index 8e39b440d..e3b847c36 100644
--- a/techlibs/xilinx/cells_xtra.sh
+++ b/techlibs/xilinx/cells_xtra.sh
@@ -116,7 +116,7 @@ function xtract_cell_decl()
 	xtract_cell_decl PS7 "(* keep *)"
 	xtract_cell_decl PULLDOWN
 	xtract_cell_decl PULLUP
-	xtract_cell_decl RAM128X1D
+	#xtract_cell_decl RAM128X1D
 	xtract_cell_decl RAM128X1S
 	xtract_cell_decl RAM256X1S
 	xtract_cell_decl RAM32M
@@ -125,7 +125,7 @@ function xtract_cell_decl()
 	xtract_cell_decl RAM32X1S_1
 	xtract_cell_decl RAM32X2S
 	xtract_cell_decl RAM64M
-	xtract_cell_decl RAM64X1D
+	x#tract_cell_decl RAM64X1D
 	xtract_cell_decl RAM64X1S
 	xtract_cell_decl RAM64X1S_1
 	xtract_cell_decl RAM64X2S
diff --git a/techlibs/xilinx/cells_xtra.v b/techlibs/xilinx/cells_xtra.v
index fbcc74682..0ec3d0df0 100644
--- a/techlibs/xilinx/cells_xtra.v
+++ b/techlibs/xilinx/cells_xtra.v
@@ -3655,17 +3655,6 @@ module PULLUP (...);
     output O;
 endmodule
 
-module RAM128X1D (...);
-    parameter [127:0] INIT = 128'h00000000000000000000000000000000;
-    parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output DPO, SPO;
-    input [6:0] A;
-    input [6:0] DPRA;
-    input D;
-    input WCLK;
-    input WE;
-endmodule
-
 module RAM128X1S (...);
     parameter [127:0] INIT = 128'h00000000000000000000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
@@ -3756,13 +3745,6 @@ module RAM64M (...);
     input WE;
 endmodule
 
-module RAM64X1D (...);
-    parameter [63:0] INIT = 64'h0000000000000000;
-    parameter [0:0] IS_WCLK_INVERTED = 1'b0;
-    output DPO, SPO;
-    input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
-endmodule
-
 module RAM64X1S (...);
     parameter [63:0] INIT = 64'h0000000000000000;
     parameter [0:0] IS_WCLK_INVERTED = 1'b0;
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 3cee81a7b..ecfb94610 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -203,9 +203,9 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		if (check_label("begin")) {
 			if (vpr)
-				run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D_ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
 			else
-				run("read_verilog -lib +/xilinx/cells_sim.v");
+				run("read_verilog -lib -D_ABC +/xilinx/cells_sim.v");
 
 			run("read_verilog -lib +/xilinx/cells_xtra.v");