From: Luke Kenneth Casson Leighton Date: Sun, 11 Jul 2021 16:09:44 +0000 (+0100) Subject: add SVREMAP new Form / Fields and CSV entry X-Git-Tag: xlen-bcd~297 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae901a0faf4e66617840047e57c8597edf39785f;p=openpower-isa.git add SVREMAP new Form / Fields and CSV entry --- diff --git a/openpower/isatables/fields.text b/openpower/isatables/fields.text index 2562f843..ec9ed008 100644 --- a/openpower/isatables/fields.text +++ b/openpower/isatables/fields.text @@ -279,6 +279,10 @@ |0 |6 |11 |16 |21 |26 |31 | | PO | SVxd | SVyd | SVzd | SVRM | XO | / | +# 1.6.34 SVRM-FORM + |0 |6 |10 |12 |14 |16 |18 |20 |26 |31 | + | PO | SVme |mi0 | mi1 | mi2 | mo0 | mo1 | rsvd | XO | / | + # 1.6.28 Instruction Fields A (6) Field used by the tbegin. instruction to specify an @@ -584,6 +588,21 @@ Section 3.3.14, 'Fixed-Point Rotate and Shift Instructions' on page 101. Formats: M + mi0 (10:11) + Field used in REMAP to select the SVSHAPE for 1st input register + Formats: SVRM + mi1 (12:13) + Field used in REMAP to select the SVSHAPE for 2nd input register + Formats: SVRM + mi2 (14:15) + Field used in REMAP to select the SVSHAPE for 3rd input register + Formats: SVRM + mo0 (16:17) + Field used in REMAP to select the SVSHAPE for 1st output register + Formats: SVRM + mo1 (18:19) + Field used in REMAP to select the SVSHAPE for 2nd output register + Formats: SVRM MO (6:10) Field used in X-form instructions to specify a sub- set of storage accesses. @@ -761,6 +780,9 @@ SVi (16:22) Simple-V immediate field for setting VL or MVL Formats: SVL + SVme (6:10) + Simple-V "REMAP" map-enable bits (0-4) + Formats: SVRM SVRM (21:25) Simple-V "REMAP" Mode Formats: SVM diff --git a/openpower/isatables/minor_22.csv b/openpower/isatables/minor_22.csv index dcc30c74..aec8c935 100644 --- a/openpower/isatables/minor_22.csv +++ b/openpower/isatables/minor_22.csv @@ -1,3 +1,4 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry out,ldst len,BR,sgn ext,upd,rsrv,32b,sgn,rc,lk,sgl pipe,comment,form,CONDITIONS 0b00000,VL,OP_SETVL,RA_OR_ZERO,NONE,NONE,RT_OR_ZERO,NONE,CR0,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,setvl,SVL, -0b00001,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svshape,SVM, +0b00001,VL,OP_SVSHAPE,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svshape,SVM, +0b00002,VL,OP_SVREMAP,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,RC,0,0,svremap,SVRM, diff --git a/src/openpower/decoder/power_enums.py b/src/openpower/decoder/power_enums.py index b9099dc2..97a5dc52 100644 --- a/src/openpower/decoder/power_enums.py +++ b/src/openpower/decoder/power_enums.py @@ -118,7 +118,8 @@ class Form(Enum): SVL = 29 # Simple-V for setvl instruction SVD = 30 # Simple-V for LD/ST bit-reverse, variant of D-Form SVDS = 31 # Simple-V for LD/ST bit-reverse, variant of DS-Form - SVM = 32 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY + SVM = 32 # Simple-V SHAPE mode - TEMPORARY TEMPORARY TEMPORARY + SVRM = 33 # Simple-V REMAP mode - TEMPORARY TEMPORARY TEMPORARY # Simple-V svp64 fields https://libre-soc.org/openpower/sv/svp64/ @@ -391,6 +392,7 @@ class MicrOp(Enum): OP_FPOP_I = 78 # temporary: replace with actual ops OP_FP_MADD = 79 OP_SVREMAP = 80 + OP_SVSHAPE = 81 @unique