From: Eddie Hung <eddie@fpgeh.com>
Date: Sun, 21 Apr 2019 21:16:59 +0000 (-0700)
Subject: Add comments
X-Git-Tag: yosys-0.9~171^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ae95aba60a573bf34034d6a70931bd55490d3f14;p=yosys.git

Add comments
---

diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index 4f02a47ea..f59c0c622 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -269,8 +269,15 @@ struct SynthXilinxPass : public Pass
 			Pass::call(design, "dff2dffe");
 
 			if (!nosrl) {
+				// shregmap operates on bit-level flops, not word-level,
+				//   so break those down here
 				Pass::call(design, "simplemap t:$dff t:$dffe");
+				// shregmap -tech xilinx can cope with $shiftx and $mux
+				//   cells for identifiying variable-length shift registers,
+				//   so attempt to convert $pmux-es to the former
 				Pass::call(design, "pmux2shiftx");
+				// pmux2shiftx can leave behind a $pmux with a single entry
+				//   -- need this to clean that up
 				Pass::call(design, "opt_expr -mux_undef");
 				Pass::call(design, "shregmap -tech xilinx -minlen 3");
 			}