From: lkcl <lkcl@web>
Date: Thu, 18 Feb 2021 16:34:00 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~155
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aeab790069c0d60c56a8f4a682eabd9029e97ad8;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index b7b8e4ee8..5d3391523 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -206,3 +206,13 @@ Note that:
   LSB of each element in the result vector
 
 Note that element width overrides are respected on the INT src or destination register (but that elwidth overrides on CRs are meaningless)
+
+# v3.1 setbc instructions
+
+there are additional setb conditional instructions in v3.1 (p129)
+
+    RT = (CR[BI] == 1) ? 1 : 0
+
+which also negate that, and also return -1 / 0.  these are similar yo crweird but not the same purpose.
+
+