From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 27 Sep 2019 18:57:53 +0000 (-0700)
Subject: Ooops AREG and BREG to default to -1
X-Git-Tag: working-ls180~1039^2~2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=aebbfffd71ab6a85f86ef44f40b1d46a7d6a60ee;p=yosys.git

Ooops AREG and BREG to default to -1
---

diff --git a/passes/pmgen/xilinx_dsp_cascade.pmg b/passes/pmgen/xilinx_dsp_cascade.pmg
index 714316808..6f4ac5849 100644
--- a/passes/pmgen/xilinx_dsp_cascade.pmg
+++ b/passes/pmgen/xilinx_dsp_cascade.pmg
@@ -146,7 +146,7 @@ code next
 endcode
 
 code argQ clock AREG
-	AREG = 0;
+	AREG = -1;
 	if (next) {
 		Cell *prev = std::get<0>(chain.back());
 		if (param(prev, \AREG, 2).as_int() > 0 &&
@@ -175,7 +175,7 @@ reject_AREG:			;
 endcode
 
 code argQ clock BREG
-	BREG = 0;
+	BREG = -1;
 	if (next) {
 		Cell *prev = std::get<0>(chain.back());
 		if (param(prev, \BREG, 2).as_int() > 0 &&